This is the patch for option B. You may not be able to test it without my next patch. At least for me selectiong EXPERT in make menuconfig breaks the build. Next patch fixes it.
Make patching cpu microcode optional (for experts). It's been requested to not link update_microcode.c in that case, and therefore we have to comment all uses. Signed-off-by: Xavi Drudis Ferran <[email protected]> --- Please apply with -p 1 --- coreboot-r6380/src/cpu/amd/model_10xxx/init_cpus.c 2011-02-25 23:54:12.000000000 +0100 +++ coreboot-disupducode/src/cpu/amd/model_10xxx/init_cpus.c 2011-02-26 01:46:19.000000000 +0100 @@ -325,7 +325,9 @@ * This happens after HTinit. * The BSP runs this code in it's own path. */ +#if CONFIG_UPDATE_CPU_MICROCODE == 1 update_microcode(cpuid_eax(1)); +#endif cpuSetAMDMSR(); #if CONFIG_SET_FIDVID diff -ru coreboot-r6380/src/cpu/amd/model_10xxx/Kconfig coreboot-disupducode/src/cpu/amd/model_10xxx/Kconfig --- coreboot-r6380/src/cpu/amd/model_10xxx/Kconfig 2011-02-25 23:54:12.000000000 +0100 +++ coreboot-disupducode/src/cpu/amd/model_10xxx/Kconfig 2011-02-26 00:59:20.000000000 +0100 @@ -50,3 +50,26 @@ endif endif + +config UPDATE_CPU_MICROCODE + bool + default y + +config UPDATE_CPU_MICROCODE + bool "Update cpu microcode" + default y + depends on EXPERT && CPU_AMD_MODEL_10XXX + help + Select this to apply non-free patches to the cpu + microcode provided by AMD to correct issues in the CPU after + production, and distributed with coreboot (not necessarily + the latest microcode version produced by AMD, but only + applied if newer than the version in your CPU). + + Unselect to let FAM10 CPUs run with the unpatched microcode + as shipped from factory. If you unselect this, no binary + microcode patches will be included in the image, so it will + help you get an image which you have the entire source code + for and may simplify license compliance. + + diff -ru coreboot-r6380/src/cpu/amd/model_10xxx/Makefile.inc coreboot-disupducode/src/cpu/amd/model_10xxx/Makefile.inc --- coreboot-r6380/src/cpu/amd/model_10xxx/Makefile.inc 2011-02-25 23:54:12.000000000 +0100 +++ coreboot-disupducode/src/cpu/amd/model_10xxx/Makefile.inc 2011-02-26 00:04:56.000000000 +0100 @@ -1,5 +1,4 @@ -# no conditionals here. If you include this file from a socket, then you get all the binaries. driver-y += model_10xxx_init.c -ramstage-y += update_microcode.c +ramstage-$(CONFIG_UPDATE_CPU_MICROCODE) += update_microcode.c ramstage-y += apic_timer.c ramstage-y += processor_name.c diff -ru coreboot-r6380/src/mainboard/amd/bimini_fam10/romstage.c coreboot-disupducode/src/mainboard/amd/bimini_fam10/romstage.c --- coreboot-r6380/src/mainboard/amd/bimini_fam10/romstage.c 2011-02-25 23:54:27.000000000 +0100 +++ coreboot-disupducode/src/mainboard/amd/bimini_fam10/romstage.c 2011-02-26 00:14:15.000000000 +0100 @@ -66,7 +66,11 @@ #include "cpu/amd/quadcore/quadcore.c" #include "cpu/amd/car/post_cache_as_ram.c" #include "cpu/amd/microcode/microcode.c" + +#if CONFIG_UPDATE_CPU_MICROCODE==1 #include "cpu/amd/model_10xxx/update_microcode.c" +#endif + #include "cpu/amd/model_10xxx/init_cpus.c" #include "northbridge/amd/amdfam10/early_ht.c" @@ -132,7 +136,10 @@ /* Setup sysinfo defaults */ set_sysinfo_in_ram(0); +#if CONFIG_UPDATE_CPU_MICROCODE==1 update_microcode(val); +#endif + post_code(0x33); cpuSetAMDMSR(); diff -ru coreboot-r6380/src/mainboard/amd/mahogany_fam10/romstage.c coreboot-disupducode/src/mainboard/amd/mahogany_fam10/romstage.c --- coreboot-r6380/src/mainboard/amd/mahogany_fam10/romstage.c 2011-02-25 23:54:27.000000000 +0100 +++ coreboot-disupducode/src/mainboard/amd/mahogany_fam10/romstage.c 2011-02-26 00:15:29.000000000 +0100 @@ -66,7 +66,11 @@ #include "cpu/amd/quadcore/quadcore.c" #include "cpu/amd/car/post_cache_as_ram.c" #include "cpu/amd/microcode/microcode.c" + +#if CONFIG_UPDATE_CPU_MICROCODE==1 #include "cpu/amd/model_10xxx/update_microcode.c" +#endif + #include "cpu/amd/model_10xxx/init_cpus.c" #include "northbridge/amd/amdfam10/early_ht.c" #include "southbridge/amd/sb700/early_setup.c" @@ -125,7 +129,11 @@ /* Setup sysinfo defaults */ set_sysinfo_in_ram(0); + +#if CONFIG_UPDATE_CPU_MICROCODE==1 update_microcode(val); +#endif + post_code(0x33); cpuSetAMDMSR(); diff -ru coreboot-r6380/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c coreboot-disupducode/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c --- coreboot-r6380/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c 2011-02-25 23:54:27.000000000 +0100 +++ coreboot-disupducode/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c 2011-02-26 00:16:25.000000000 +0100 @@ -87,7 +87,11 @@ #include "cpu/amd/quadcore/quadcore.c" #include "cpu/amd/car/post_cache_as_ram.c" #include "cpu/amd/microcode/microcode.c" + +#if CONFIG_UPDATE_CPU_MICROCODE==1 #include "cpu/amd/model_10xxx/update_microcode.c" +#endif + #include "cpu/amd/model_10xxx/init_cpus.c" #include "northbridge/amd/amdfam10/early_ht.c" @@ -227,7 +231,11 @@ /* Setup sysinfo defaults */ set_sysinfo_in_ram(0); + +#if CONFIG_UPDATE_CPU_MICROCODE==1 update_microcode(val); +#endif + post_code(0x33); cpuSetAMDMSR(); diff -ru coreboot-r6380/src/mainboard/amd/tilapia_fam10/romstage.c coreboot-disupducode/src/mainboard/amd/tilapia_fam10/romstage.c --- coreboot-r6380/src/mainboard/amd/tilapia_fam10/romstage.c 2011-02-25 23:54:27.000000000 +0100 +++ coreboot-disupducode/src/mainboard/amd/tilapia_fam10/romstage.c 2011-02-26 00:14:55.000000000 +0100 @@ -65,7 +65,11 @@ #include "cpu/amd/quadcore/quadcore.c" #include "cpu/amd/car/post_cache_as_ram.c" #include "cpu/amd/microcode/microcode.c" + +#if CONFIG_UPDATE_CPU_MICROCODE==1 #include "cpu/amd/model_10xxx/update_microcode.c" +#endif + #include "cpu/amd/model_10xxx/init_cpus.c" #include "northbridge/amd/amdfam10/early_ht.c" #include <spd.h> @@ -124,7 +128,10 @@ /* Setup sysinfo defaults */ set_sysinfo_in_ram(0); +#if CONFIG_UPDATE_CPU_MICROCODE==1 update_microcode(val); +#endif + post_code(0x33); cpuSetAMDMSR(); diff -ru coreboot-r6380/src/mainboard/asus/m4a785-m/romstage.c coreboot-disupducode/src/mainboard/asus/m4a785-m/romstage.c --- coreboot-r6380/src/mainboard/asus/m4a785-m/romstage.c 2011-02-25 23:54:23.000000000 +0100 +++ coreboot-disupducode/src/mainboard/asus/m4a785-m/romstage.c 2011-02-26 00:10:18.000000000 +0100 @@ -65,7 +65,11 @@ #include "cpu/amd/quadcore/quadcore.c" #include "cpu/amd/car/post_cache_as_ram.c" #include "cpu/amd/microcode/microcode.c" + +#if CONFIG_UPDATE_CPU_MICROCODE==1 #include "cpu/amd/model_10xxx/update_microcode.c" +#endif + #include "cpu/amd/model_10xxx/init_cpus.c" #include "northbridge/amd/amdfam10/early_ht.c" #include <spd.h> @@ -125,7 +129,10 @@ /* Setup sysinfo defaults */ set_sysinfo_in_ram(0); +#if CONFIG_UPDATE_CPU_MICROCODE==1 update_microcode(val); +#endif + post_code(0x33); cpuSetAMDMSR(); diff -ru coreboot-r6380/src/mainboard/asus/m4a78-em/romstage.c coreboot-disupducode/src/mainboard/asus/m4a78-em/romstage.c --- coreboot-r6380/src/mainboard/asus/m4a78-em/romstage.c 2011-02-25 23:54:24.000000000 +0100 +++ coreboot-disupducode/src/mainboard/asus/m4a78-em/romstage.c 2011-02-26 00:11:40.000000000 +0100 @@ -65,7 +65,11 @@ #include "cpu/amd/quadcore/quadcore.c" #include "cpu/amd/car/post_cache_as_ram.c" #include "cpu/amd/microcode/microcode.c" + +#if CONFIG_UPDATE_CPU_MICROCODE==1 #include "cpu/amd/model_10xxx/update_microcode.c" +#endif + #include "cpu/amd/model_10xxx/init_cpus.c" #include "northbridge/amd/amdfam10/early_ht.c" #include <spd.h> @@ -125,7 +129,11 @@ /* Setup sysinfo defaults */ set_sysinfo_in_ram(0); + +#if CONFIG_UPDATE_CPU_MICROCODE==1 update_microcode(val); +#endif + post_code(0x33); cpuSetAMDMSR(); diff -ru coreboot-r6380/src/mainboard/gigabyte/ma785gmt/romstage.c coreboot-disupducode/src/mainboard/gigabyte/ma785gmt/romstage.c --- coreboot-r6380/src/mainboard/gigabyte/ma785gmt/romstage.c 2011-02-25 23:54:23.000000000 +0100 +++ coreboot-disupducode/src/mainboard/gigabyte/ma785gmt/romstage.c 2011-02-26 00:19:20.000000000 +0100 @@ -61,7 +61,11 @@ #include "cpu/amd/quadcore/quadcore.c" #include "cpu/amd/car/post_cache_as_ram.c" #include "cpu/amd/microcode/microcode.c" + +#if CONFIG_UPDATE_CPU_MICROCODE==1 #include "cpu/amd/model_10xxx/update_microcode.c" +#endif + #include "cpu/amd/model_10xxx/init_cpus.c" #include "northbridge/amd/amdfam10/early_ht.c" #include <spd.h> @@ -121,7 +125,10 @@ /* Setup sysinfo defaults */ set_sysinfo_in_ram(0); + +#if CONFIG_UPDATE_CPU_MICROCODE==1 update_microcode(val); +#endif post_code(0x33); cpuSetAMDMSR(); diff -ru coreboot-r6380/src/mainboard/gigabyte/ma78gm/romstage.c coreboot-disupducode/src/mainboard/gigabyte/ma78gm/romstage.c --- coreboot-r6380/src/mainboard/gigabyte/ma78gm/romstage.c 2011-02-25 23:54:23.000000000 +0100 +++ coreboot-disupducode/src/mainboard/gigabyte/ma78gm/romstage.c 2011-02-26 00:18:33.000000000 +0100 @@ -65,7 +65,11 @@ #include "cpu/amd/quadcore/quadcore.c" #include "cpu/amd/car/post_cache_as_ram.c" #include "cpu/amd/microcode/microcode.c" + +#if CONFIG_UPDATE_CPU_MICROCODE==1 #include "cpu/amd/model_10xxx/update_microcode.c" +#endif + #include "cpu/amd/model_10xxx/init_cpus.c" #include "northbridge/amd/amdfam10/early_ht.c" #include <spd.h> @@ -123,7 +127,11 @@ /* Setup sysinfo defaults */ set_sysinfo_in_ram(0); + +#if CONFIG_UPDATE_CPU_MICROCODE==1 update_microcode(val); +#endif + post_code(0x33); cpuSetAMDMSR(); diff -ru coreboot-r6380/src/mainboard/hp/dl165_g6_fam10/romstage.c coreboot-disupducode/src/mainboard/hp/dl165_g6_fam10/romstage.c --- coreboot-r6380/src/mainboard/hp/dl165_g6_fam10/romstage.c 2011-02-25 23:54:25.000000000 +0100 +++ coreboot-disupducode/src/mainboard/hp/dl165_g6_fam10/romstage.c 2011-02-26 00:09:06.000000000 +0100 @@ -82,7 +82,11 @@ #include "cpu/amd/quadcore/quadcore.c" #include "cpu/amd/car/post_cache_as_ram.c" #include "cpu/amd/microcode/microcode.c" + +#if CONFIG_UPDATE_CPU_MICROCODE==1 #include "cpu/amd/model_10xxx/update_microcode.c" +#endif + #include "cpu/amd/model_10xxx/init_cpus.c" #include "northbridge/amd/amdfam10/early_ht.c" @@ -136,7 +140,10 @@ /* Setup sysinfo defaults */ set_sysinfo_in_ram(0); +#if CONFIG_UPDATE_CPU_MICROCODE==1 update_microcode(val); +#endif + post_code(0x33); cpuSetAMDMSR(); diff -ru coreboot-r6380/src/mainboard/iei/kino-780am2-fam10/romstage.c coreboot-disupducode/src/mainboard/iei/kino-780am2-fam10/romstage.c --- coreboot-r6380/src/mainboard/iei/kino-780am2-fam10/romstage.c 2011-02-25 23:54:26.000000000 +0100 +++ coreboot-disupducode/src/mainboard/iei/kino-780am2-fam10/romstage.c 2011-02-26 00:19:45.000000000 +0100 @@ -67,7 +67,11 @@ #include "cpu/amd/quadcore/quadcore.c" #include "cpu/amd/car/post_cache_as_ram.c" #include "cpu/amd/microcode/microcode.c" + +#if CONFIG_UPDATE_CPU_MICROCODE==1 #include "cpu/amd/model_10xxx/update_microcode.c" +#endif + #include "cpu/amd/model_10xxx/init_cpus.c" #include "northbridge/amd/amdfam10/early_ht.c" #include <spd.h> @@ -126,7 +130,11 @@ /* Setup sysinfo defaults */ set_sysinfo_in_ram(0); + +#if CONFIG_UPDATE_CPU_MICROCODE==1 update_microcode(val); +#endif + post_code(0x33); cpuSetAMDMSR(); diff -ru coreboot-r6380/src/mainboard/jetway/pa78vm5/romstage.c coreboot-disupducode/src/mainboard/jetway/pa78vm5/romstage.c --- coreboot-r6380/src/mainboard/jetway/pa78vm5/romstage.c 2011-02-25 23:54:26.000000000 +0100 +++ coreboot-disupducode/src/mainboard/jetway/pa78vm5/romstage.c 2011-02-26 00:09:34.000000000 +0100 @@ -72,7 +72,11 @@ #include "cpu/amd/quadcore/quadcore.c" #include "cpu/amd/car/post_cache_as_ram.c" #include "cpu/amd/microcode/microcode.c" + +#if CONFIG_UPDATE_CPU_MICROCODE==1 #include "cpu/amd/model_10xxx/update_microcode.c" +#endif + #include "cpu/amd/model_10xxx/init_cpus.c" #include "northbridge/amd/amdfam10/early_ht.c" #include <spd.h> @@ -131,7 +135,10 @@ /* Setup sysinfo defaults */ set_sysinfo_in_ram(0); +#if CONFIG_UPDATE_CPU_MICROCODE==1 update_microcode(val); +#endif + post_code(0x33); cpuSetAMDMSR(); diff -ru coreboot-r6380/src/mainboard/msi/ms9652_fam10/romstage.c coreboot-disupducode/src/mainboard/msi/ms9652_fam10/romstage.c --- coreboot-r6380/src/mainboard/msi/ms9652_fam10/romstage.c 2011-02-25 23:54:23.000000000 +0100 +++ coreboot-disupducode/src/mainboard/msi/ms9652_fam10/romstage.c 2011-02-26 00:13:49.000000000 +0100 @@ -76,7 +76,11 @@ #include "southbridge/nvidia/mcp55/early_setup_car.c" #include "cpu/amd/car/post_cache_as_ram.c" #include "cpu/amd/microcode/microcode.c" + +#if CONFIG_UPDATE_CPU_MICROCODE==1 #include "cpu/amd/model_10xxx/update_microcode.c" +#endif + #include "cpu/amd/model_10xxx/init_cpus.c" #include "northbridge/amd/amdfam10/early_ht.c" @@ -153,7 +157,11 @@ /* Setup sysinfo defaults */ set_sysinfo_in_ram(0); + +#if CONFIG_UPDATE_CPU_MICROCODE==1 update_microcode(val); +#endif + post_code(0x33); cpuSetAMDMSR(); diff -ru coreboot-r6380/src/mainboard/supermicro/h8dmr_fam10/romstage.c coreboot-disupducode/src/mainboard/supermicro/h8dmr_fam10/romstage.c --- coreboot-r6380/src/mainboard/supermicro/h8dmr_fam10/romstage.c 2011-02-25 23:54:25.000000000 +0100 +++ coreboot-disupducode/src/mainboard/supermicro/h8dmr_fam10/romstage.c 2011-02-26 00:18:07.000000000 +0100 @@ -68,7 +68,11 @@ #include "southbridge/nvidia/mcp55/early_setup_car.c" #include "cpu/amd/car/post_cache_as_ram.c" #include "cpu/amd/microcode/microcode.c" + +#if CONFIG_UPDATE_CPU_MICROCODE==1 #include "cpu/amd/model_10xxx/update_microcode.c" +#endif + #include "cpu/amd/model_10xxx/init_cpus.c" #include "northbridge/amd/amdfam10/early_ht.c" @@ -145,7 +149,11 @@ /* Setup sysinfo defaults */ set_sysinfo_in_ram(0); + +#if CONFIG_UPDATE_CPU_MICROCODE==1 update_microcode(val); +#endif + post_code(0x33); cpuSetAMDMSR(); diff -ru coreboot-r6380/src/mainboard/supermicro/h8qme_fam10/romstage.c coreboot-disupducode/src/mainboard/supermicro/h8qme_fam10/romstage.c --- coreboot-r6380/src/mainboard/supermicro/h8qme_fam10/romstage.c 2011-02-25 23:54:25.000000000 +0100 +++ coreboot-disupducode/src/mainboard/supermicro/h8qme_fam10/romstage.c 2011-02-26 00:17:34.000000000 +0100 @@ -74,7 +74,11 @@ #include "southbridge/nvidia/mcp55/early_setup_car.c" #include "cpu/amd/car/post_cache_as_ram.c" #include "cpu/amd/microcode/microcode.c" + +#if CONFIG_UPDATE_CPU_MICROCODE==1 #include "cpu/amd/model_10xxx/update_microcode.c" +#endif + #include "cpu/amd/model_10xxx/init_cpus.c" #include "northbridge/amd/amdfam10/early_ht.c" @@ -197,7 +201,11 @@ /* Setup sysinfo defaults */ set_sysinfo_in_ram(0); + +#if CONFIG_UPDATE_CPU_MICROCODE==1 update_microcode(val); +#endif + post_code(0x33); cpuSetAMDMSR(); diff -ru coreboot-r6380/src/mainboard/tyan/s2912_fam10/romstage.c coreboot-disupducode/src/mainboard/tyan/s2912_fam10/romstage.c --- coreboot-r6380/src/mainboard/tyan/s2912_fam10/romstage.c 2011-02-25 23:54:28.000000000 +0100 +++ coreboot-disupducode/src/mainboard/tyan/s2912_fam10/romstage.c 2011-02-26 00:13:09.000000000 +0100 @@ -77,7 +77,11 @@ #include "southbridge/nvidia/mcp55/early_setup_car.c" #include "cpu/amd/car/post_cache_as_ram.c" #include "cpu/amd/microcode/microcode.c" + +#if CONFIG_UPDATE_CPU_MICROCODE==1 #include "cpu/amd/model_10xxx/update_microcode.c" +#endif + #include "cpu/amd/model_10xxx/init_cpus.c" #include "northbridge/amd/amdfam10/early_ht.c" @@ -153,7 +157,11 @@ /* Setup sysinfo defaults */ set_sysinfo_in_ram(0); + +#if CONFIG_UPDATE_CPU_MICROCODE==1 update_microcode(val); +#endif + post_code(0x33); cpuSetAMDMSR();
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