Author: svens Date: Tue May 3 09:55:30 2011 New Revision: 6553 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6553
Log: i82801gx: enable SPI prefetching Signed-off-by: Sven Schnelle <[email protected]> Acked-by: Sven Schnelle <[email protected]> Added: trunk/src/southbridge/intel/i82801gx/bootblock.c Modified: trunk/src/southbridge/intel/i82801gx/Kconfig Modified: trunk/src/southbridge/intel/i82801gx/Kconfig ============================================================================== --- trunk/src/southbridge/intel/i82801gx/Kconfig Mon May 2 21:53:04 2011 (r6552) +++ trunk/src/southbridge/intel/i82801gx/Kconfig Tue May 3 09:55:30 2011 (r6553) @@ -38,5 +38,10 @@ int default 1 +config BOOTBLOCK_SOUTHBRIDGE_INIT + string + default "southbridge/intel/i82801gx/bootblock.c" + depends on SOUTHBRIDGE_INTEL_I82801GX + endif Added: trunk/src/southbridge/intel/i82801gx/bootblock.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/southbridge/intel/i82801gx/bootblock.c Tue May 3 09:55:30 2011 (r6553) @@ -0,0 +1,40 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Sven Schnelle <[email protected]> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <arch/romcc_io.h> + +static void enable_spi_prefetch(void) +{ + u8 reg8; + device_t dev; + + dev = PCI_DEV(0, 0x1f, 0); + + reg8 = pci_read_config8(dev, 0xdc); + reg8 &= ~(3 << 2); + reg8 |= (2 << 2); /* Prefetching and Caching Enabled */ + pci_write_config8(dev, 0xdc, reg8); +} + +static void bootblock_southbridge_init(void) +{ + enable_spi_prefetch(); +} + -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
