Marshall Buschman ([email protected]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/21
-gerrit
commit 8e11b366fe5aaf5fb16942bca5f0d837d4cb427a Author: Marshall Buschman <[email protected]> Date: Fri Jun 10 21:19:55 2011 -0500 Move SB800 clock init earlier Committing Scott's e350m1 changes (svn r6585): Move SB800 clock init earlier, Fixes problem where initial serial port output is garbled. Change-Id: I30342e9c5ef1f65a45afad66b330ee817a604599 Signed-off-by: Scott Duplichan <[email protected]> Signed-off-by: Marshall Buschman <[email protected]> diff --git a/src/mainboard/asrock/e350m1/romstage.c b/src/mainboard/asrock/e350m1/romstage.c index 7d25ec1..aaaaee4 100644 --- a/src/mainboard/asrock/e350m1/romstage.c +++ b/src/mainboard/asrock/e350m1/romstage.c @@ -55,6 +55,20 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) // all cores: set pstate 0 (1600 MHz) early to save a few ms of boot time __writemsr(0xc0010062, 0); + if (boot_cpu()) { + u8 reg8; + // SB800: program AcpiMmioEn to enable MMIO access to MiscCntrl register + outb(0x24, 0xCD6); + reg8 = inb(0xCD7); + reg8 |= 1; + reg8 &= ~(1 << 1); + outb(reg8, 0xCD7); + + // program SB800 MiscCntrl + *(volatile u32 *)(0xFED80000+0xE00+0x40) &= ~((1 << 0) | (1 << 2)); /* 48Mhz */ + *(volatile u32 *)(0xFED80000+0xE00+0x40) |= 1 << 1; /* 48Mhz */ + } + // early enable of PrefetchEnSPIFromHost if (boot_cpu()) { __outdword(0xcf8, 0x8000a3b8);
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