Marshall Buschman ([email protected]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/22
-gerrit
commit 3218571ad2ebbafd9fa03d16fa2c9fe91c647025 Author: Marshall Buschman <[email protected]> Date: Fri Jun 10 21:42:21 2011 -0500 Really move SB800 clock init earlier Move SB800 clock init code, not copy it. Doh! Change-Id: I1b1bd36b7c1bd85d879544b014d81c55a94916b9 Signed-off-by: Marshall Buschman <[email protected]> diff --git a/src/mainboard/asrock/e350m1/romstage.c b/src/mainboard/asrock/e350m1/romstage.c index aaaaee4..351bf51 100644 --- a/src/mainboard/asrock/e350m1/romstage.c +++ b/src/mainboard/asrock/e350m1/romstage.c @@ -94,17 +94,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); } - //reg8 = pmio_read(0x24); - outb(0x24, 0xCD6); - reg8 = inb(0xCD7); - reg8 |= 1; - reg8 &= ~(1 << 1); - //pmio_write(0x24, reg8); - outb(0x24, 0xCD6); - outb(reg8, 0xCD7); - - *(volatile u32 *)(0xFED80000 + 0xE00 + 0x40) &= ~((1 << 0) | (1 << 2)); /* 48Mhz */ - *(volatile u32 *)(0xFED80000 + 0xE00 + 0x40) |= 1 << 1; /* 48Mhz */ /* Halt if there was a built in self test failure */ post_code(0x34);
-- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
