Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/368
-gerrit commit 26240769d6dac8bc6606e839daafbabd06474a0b Author: Florian Zumbiehl <[email protected]> Date: Tue Nov 1 20:16:16 2011 +0100 in vt8237r_enable(), write function enables only to ISA bridge config space vt8237r_enable() so far wrote the function enable values to the same offset in the config space of every one of the vt8237's functions, even though the register is located in the ISA bridge only. Change-Id: I639586dc238132f5b8d2f320b794948718281b9c Signed-off-by: Florian Zumbiehl <[email protected]> --- src/southbridge/via/vt8237r/vt8237r.c | 6 ++++-- 1 files changed, 4 insertions(+), 2 deletions(-) diff --git a/src/southbridge/via/vt8237r/vt8237r.c b/src/southbridge/via/vt8237r/vt8237r.c index 5ba3815..a0aafa7 100644 --- a/src/southbridge/via/vt8237r/vt8237r.c +++ b/src/southbridge/via/vt8237r/vt8237r.c @@ -69,8 +69,10 @@ static void vt8237r_enable(struct device *dev) struct southbridge_via_vt8237r_config *sb = (struct southbridge_via_vt8237r_config *)dev->chip_info; - pci_write_config8(dev, 0x50, sb->fn_ctrl_lo); - pci_write_config8(dev, 0x51, sb->fn_ctrl_hi); + if (dev->path.type == DEVICE_PATH_PCI && dev->path.pci.devfn == PCI_DEVFN(0x11,0)) { + pci_write_config8(dev, 0x50, sb->fn_ctrl_lo); + pci_write_config8(dev, 0x51, sb->fn_ctrl_hi); + } /* TODO: If SATA is disabled, move IDE to fn0 to conform PCI specs. */ } -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
