On Monday 23 January 2012 20:12:33 Prakash Punnoor wrote: > Hi, > > as a noob I am trying to make a port based on the mahagony fam10, as the > abit is also an AMD RS780/SB700 board. I have a Phenom II X4 840 installed, > so I guess selecting fam10 is correct? I also adjusted the sources to use > the correct superio (Winbond W83627DHG). Unfortunately the motherboard > doesn't have serial ports, so I am debugging using a port80 diagnostics > card... (Should I actually enable the com ports in devicetree.cb?) > > So, I cannot make coreboot boot. On cold start it seems to hang in > > src/southbridge/amd/sb700/reset.c > > in soft_reset. set_bios_reset seems sucessful, but I get no post code after > outb(0x06, 0x0cf9). Any idea, what I can try? > > If I do a warm start (ie: booting with factory bios, flashing coreboot image > and then reset) I get further, but it hangs somewhere in dev_enable. > Probably my set_pcie_dereset and/or my devicetree.cb is wrong? How to find > out the correct GPIOs for the former?
Well, I came a bit further I found out the hang here was because of missing
"device id" of my cpu. This solves that problem:
diff --git a/src/cpu/amd/model_10xxx/model_10xxx_init.c
b/src/cpu/amd/model_10xxx/model_10xxx_init.c
index cf11135..24da249 100644
--- a/src/cpu/amd/model_10xxx/model_10xxx_init.c
+++ b/src/cpu/amd/model_10xxx/model_10xxx_init.c
@@ -153,6 +153,7 @@ static struct cpu_device_id cpu_table[] = {
{ X86_VENDOR_AMD, 0x100F42 }, /* RB-C2 */
{ X86_VENDOR_AMD, 0x100F43 }, /* RB-C3 */
{ X86_VENDOR_AMD, 0x100F52 }, /* BL-C2 */
+ { X86_VENDOR_AMD, 0x100F53 }, /* BL-C3 */
{ X86_VENDOR_AMD, 0x100F62 }, /* DA-C2 */
{ X86_VENDOR_AMD, 0x100F63 }, /* DA-C3 */
{ X86_VENDOR_AMD, 0x100F80 }, /* HY-D0 */
Ignoring the soft_reset problem, now coreboot seems to successfully finish.
The last post code is F8, so it seesm SeaBios should have been started.
Unfortunately I the internal gfx doesn't seem to get propery initialized, as I
cannot see anything. Then I changed to config to coreboot running vga option
ROM and using grub2 as payload. On "warm start" coreboot now resets itself
indefinitely. On cold start, coreboot want to do a soft reset - which still
hangs. I think the soft reset here gets triggered by init_cpus. (I haven't
verified this, yet.)
I am still not sure about the GPIO/GPM to use for dereset. At least GPM 8 and
9 and GPIO 73 look "fishy", ie the registers contain non default values, so I
tried using them for dereset:
void set_pci_de_reset(int enable)
{
u8 byte;
u16 word;
device_t sm_dev;
/* set 0 to bit1 :disable GPM9 as SLP_S2 output */
/* set 0 to bit2 :disable GPM8 as AZ_RST output */
byte = pm_ioread(0x8d);
byte &= ~((1 << 1) | (1 << 2));
pm_iowrite(0x8d, byte);
/* set the GPM8 and GPM9 output enable and the value to 1 */
byte = pm_ioread(0x94);
byte &= ~((1 << 2) | (1 << 3));
if (enable)
byte |= ((1 << 0) | (1 << 1));
else
byte &= ~((1 << 0) | (1 << 1));
pm_iowrite(0x94, byte);
sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
word = pci_read_config16(sm_dev, 0x5A);
if (enable)
word |= (1 << 3); /* GPIO 73 */
else
word &= ~(1 << 3);
word &= ~(1 << 7);
word |= (1 << 15);
pci_write_config16(sm_dev, 0x5A, word);
}
void set_pcie_dereset()
{
set_pci_de_reset(1);
}
void set_pcie_reset()
{
set_pci_de_reset(0);
}
Attached is my devicetree.cb. The dual slot, gpp and gppsb config I read out
from nbmisc registers.
Any help would be appreciated.
Regards,
Prakash#Define gpp_configuration, A=0, B=1, C=2, D=3, E=4(default)
#Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7)
#Define gfx_dev2_dev3, 0: a link will never be established on Dev2 or Dev3,
# 1: the system allows a PCIE link to be established on
Dev2 or Dev3.
#Define gfx_dual_slot, 0: single slot, 1: dual slot
#Define gfx_lane_reversal, 0: disable lane reversal, 1: enable
#Define gfx_tmds, 0: didn't support TMDS, 1: support
#Define gfx_compliance, 0: didn't support compliance, 1: support
#Define gfx_reconfiguration, 0: short reconfiguration, 1(default): long
reconfiguration
#Define gfx_link_width, 0: x16, 1: x1, 2: x2, 3: x4, 4: x8, 5: x12 (not
supported), 6: x16
chip northbridge/amd/amdfam10/root_complex
device lapic_cluster 0 on
chip cpu/amd/socket_AM2r2
device lapic 0 on end
end
end
device pci_domain 0 on
subsystemid 0x1022 0x3060 inherit
chip northbridge/amd/amdfam10
device pci 18.0 on # northbridge
chip southbridge/amd/rs780
device pci 0.0 on end # HT 0x9600
device pci 1.0 on end # Internal
Graphics P2P bridge 0x9602
device pci 2.0 on end # PCIE P2P bridge
(external graphics) 0x9603
device pci 3.0 on end # PCIE P2P bridge
0x960b
device pci 4.0 on end # PCIE P2P bridge
0x9604
device pci 5.0 off end # PCIE P2P
bridge 0x9605
device pci 6.0 off end # PCIE P2P
bridge 0x9606
device pci 7.0 off end # PCIE P2P
bridge 0x9607
device pci 8.0 off end # NB/SB Link P2P
bridge
device pci 9.0 on end #
device pci a.0 on end #
register "gppsb_configuration" = "4"
# Configuration E default
register "gpp_configuration" = "3" #
Configuration D default
register "port_enable" = "0x6fc"
register "gfx_dev2_dev3" = "1"
register "gfx_dual_slot" = "0"
register "gfx_lane_reversal" = "0"
register "gfx_tmds" = "0"
register "gfx_compliance" = "0"
register "gfx_reconfiguration" = "1"
register "gfx_link_width" = "0"
end
chip southbridge/amd/sb700 # it is under NB/SB
Link, but on the same pri bus
device pci 11.0 on end # SATA
device pci 12.0 on end # USB
device pci 12.1 on end # USB
device pci 12.2 on end # USB
device pci 13.0 on end # USB
device pci 13.1 on end # USB
device pci 13.2 on end # USB
device pci 14.0 on # SM
chip drivers/generic/generic
#dimm 0-0-0
device i2c 50 on end
end
chip drivers/generic/generic
#dimm 0-0-1
device i2c 51 on end
end
chip drivers/generic/generic
#dimm 0-1-0
device i2c 52 on end
end
chip drivers/generic/generic
#dimm 0-1-1
device i2c 53 on end
end
end # SM
device pci 14.1 on end # IDE 0x439c
device pci 14.2 on end # HDA 0x4383
device pci 14.3 on # LPC 0x439d
chip superio/winbond/w83627dhg
device pnp 2e.0 off #
Floppy
io 0x60 = 0x3f0
irq 0x70 = 6
drq 0x74 = 2
end
device pnp 2e.1 off #
Parallel Port
io 0x60 = 0x378
irq 0x70 = 7
end
device pnp 2e.2 on #
Com1
io 0x60 = 0x3f8
irq 0x70 = 4
end
device pnp 2e.3 on #
Com2
io 0x60 = 0x2f8
irq 0x70 = 3
end
device pnp 2e.5 on #
PS/2 keyboard & mouse
io 0x60 = 0x60
io 0x62 = 0x64
irq 0x70 = 1
end
#device pnp 2e.6 off #
SPI
#end
device pnp 2e.307 off #
GPIO6
end
device pnp 2e.8 on #
WDTO#, PLED
end
device pnp 2e.009 on #
GPIO2
end
device pnp 2e.109 on #
GPIO3
end
device pnp 2e.209 on #
GPIO4
end
device pnp 2e.309 off #
GPIO5
end
device pnp 2e.a off #
ACPI
end
device pnp 2e.b on # HWM
io 0x60 = 0x290
end
device pnp 2e.c off #
PECI, SST
end
end
#superio/winbond/w83627dhg
end #LPC
device pci 14.4 on end # PCI 0x4384
device pci 14.5 off end # USB 2
register "boot_switch_sata_ide" = "0"
# 0: boot from SATA. 1: IDE
end #southbridge/amd/sb700
end # device pci 18.0
device pci 18.0 on end
device pci 18.0 on end
device pci 18.1 on end
device pci 18.2 on end
device pci 18.3 on end
device pci 18.4 on end
end #northbridge/amd/amdk8
end #pci_domain
end #northbridge/amd/amdk8/root_complex
signature.asc
Description: This is a digitally signed message part.
-- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
