Paul Geraedts wrote: > My hardware target is the Papilio platform in general [1];
I have one as well, can try to help test. > All current Papilio implementations (to which I count the OLS) rely > on UART over USB. They rely on UART, not USB. FPGA on OLS as well as Papilio has no idea that there is a USB connection at all. > I will try to make my VHDL cores so they will be compatible with > both types of boards. I plan to start with UART over USB support > for the currently available Papilio boards. UART is stoneage idiotic useless. It's 2012, so please aim higher. > Basically flashrom SPI access, POST code access and serial console > access. This 'playground' should eventually give me enough insight > in an optimal implementation when targeting future boards. Don't invent yet another packet protocol on top of a serial stream, do this right the first time. You're planning on implementing three different functions, and they really do need to use different interfaces. > At the moment I'm working towards a prototype of the hardware. The Papilio already has everything ready, except for useful host IO. The UART is stupid. I suggest that you focus on one core at a time, and only combine them together later, when there is a useful host interface. //Peter -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
