Dear coreboot folks,
Am Donnerstag, den 18.04.2013, 19:58 +0200 schrieb Stefan Tauner: > andor reported a problem where flashrom does reproducibly not work with > coreboot but does with the vendor BIOS > http://paste.flashrom.org/view.php?id=1614 > > Apparently it is related to fast reads and/or the frequency. > We have forced the fastReadEnable bit in the SPI_Cntrl0 from 1 to 0 and > also set NormSpeed in SPI_Cntrl1 to 16.5 Mhz (previously was 0 i.e. 66 > MHz) in flashrom and the problem vanished. > > Coreboot hard codes the fast read setting in > src/southbridge/amd/cimx/sb800/bootblock.c: > > static void enable_spi_fast_mode(void) > { > u8 byte; > u32 dword; > device_t dev = PCI_DEV(0, 0x14, 0x03); > > // set temp MMIO base > volatile u32 *spi_base = (void *)0xa0000000; > u32 save = pci_io_read_config32(dev, 0xa0); > pci_io_write_config32(dev, 0xa0, (u32) spi_base | 2); > > // early enable of SPI 33 MHz fast mode read > byte = spi_base[3]; > spi_base[3] = (byte & ~(3 << 14)) | (1 << 14); > spi_base[0] = spi_base[0] | (1 << 18); // fast read enable > > pci_io_write_config32(dev, 0xa0, save); > } > > Marc suggested that this should be configurable in the devicetree or by > a kconfig setting. Also, the statements using "byte" do not make a lot > of sense to me. Shouldn't that be a u32 instead? > > The public documentation of the fastReadEnable is lacking any detail > and I don't have access to the NDAed version of the RRG. Is my theory > correct that the controller uses the 0x0B opcode with a fixed frequency > (33 MHz?) instead of 0x03 with the frequency set by NormSpeed? MacGyver reported the same problems with the MXIC MX25L3206EPI in #coreboot on <irc.freenode.net>. In the end after several hours, Kyösti was the one remembering the problem reported by Stefan – though Andor had it with a W25Q64 chip – and Kyösti even submitted a patch to Gerrit [1]. Unfortunately MacGyver reports that it does not fix his problem yet, although the NormSpeed problem seems fixed. Thanks, Paul PS: No idea, if the flashrom mailing list should be put in CC. [1] http://review.coreboot.org/#/c/5089/
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