Am Donnerstag, den 20.03.2014, 22:33 +0100 schrieb Stefan Reinauer: > Appendix A: romcc boards to be removed > bifferos/bifferboard > dmp/vortex86ex These are unfortunate, since they're relatively new ports (and one of them by the vendor, no less!).
I hope their RAM init is relatively simple - in that case, it might be possible to restrict romcc use to their northbridge code, without affecting common coreboot code. Patrick
signature.asc
Description: This is a digitally signed message part
-- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
