On Thu, 2015-03-12 at 10:02 +0100, Patrick Agrain wrote: > Hello, > > More on this topic. > Kyösti, as required, here are the info. > > - I'm able to boot a Linux OS with (internal) uart1 from Atom. > - I'm also to boot the Linux with following command-line : kernel > /boot/vmlinuz-2.6.32-xx-dhs3 root=/dev/sda2 > console=uart8250,mmio,0xdf601000,115200n8 panic=5. The kernel logs are then > sent to the external UART, > as soon as the serial driver is loaded.. So far so good... >
Ok, just checking. I need to correct my previous statement in that I do not know anyone (yet) using OxPCIe with the specific intel chipset you have there, but an older one. It is possible those PCI-e root ports are not yet initialized/trained when we attempt the PCI ID detection for the UART card. > Here are the lspci information from a Mohon Peak. > [root@mohon_peak ~]# lspci -t > -[0000:00]-+-00.0 > +-01.0-[01]----00.0 > +-03.0-[02-06]----00.0-[03-06]--+-04.0-[04]-- > | +-05.0-[05]--+-00.0 > | | \-00.1 > | \-08.0-[06]-- > +-0e.0 > +-0f.0 > +-13.0 > +-14.0 > +-14.1 > +-16.0 > +-17.0 > +-18.0 > +-1f.0 > \-1f.3 > [root@mohon_peak ~]# > [root@mohon_peak ~]# lspci -vv -d 1415:c158 > 01:00.0 Serial controller: Oxford Semiconductor Ltd OXPCIe952 Dual 16C950 > UART (prog-if 02 [16550]) > Subsystem: Oxford Semiconductor Ltd OXPCIe952 Dual 16C950 UART > Control: I/O- Mem+ BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- > Stepping- SERR- FastB2B- DisINTx- > Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- > <TAbort- <MAbort- >SERR- <PERR- INTx- > Interrupt: pin A routed to IRQ 16 > Region 0: Memory at df600000 (32-bit, non-prefetchable) [size=16K] > Region 1: Memory at df200000 (32-bit, non-prefetchable) [size=2M] > Region 2: Memory at df400000 (32-bit, non-prefetchable) [size=2M] > Capabilities: [40] Power Management version 3 > Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=55mA > PME(D0-,D1+,D2+,D3hot+,D3cold+) > Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME- > Capabilities: [70] Express (v1) Endpoint, MSI 00 > DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s > <128ns, L1 <2us > ExtTag- AttnBtn- AttnInd- PwrInd- RBE+ FLReset- > DevCtl: Report errors: Correctable- Non-Fatal- Fatal- > Unsupported- > RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop- > MaxPayload 128 bytes, MaxReadReq 512 bytes > DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr+ > TransPend- > LnkCap: Port #0, Speed 2.5GT/s, Width x1, ASPM L0s L1, > Latency L0 unlimited, L1 unlimited > ClockPM+ Surprise- LLActRep- BwNot- > LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- > CommClk+ > ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- > LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ > DLActive- BWMgmt- ABWMgmt- > Capabilities: [b0] MSI-X: Enable- Count=16 Masked- > Vector table: BAR=1 offset=001b3000 > PBA: BAR=1 offset=001b2000 > Capabilities: [100 v1] Device Serial Number 00-30-e0-11-11-00-01-50 > Capabilities: [110 v1] Power Budgeting <?> > Kernel driver in use: serial > I think EARLY_PCI parameters are fine if you also assigned MMIO_BASE with 0xdf000000. > [root@mohon_peak ~]# > [root@mohon_peak ~]# dmesg | grep tty > serial8250: ttyS0 at I/O 0x3f8 (irq = 4) is a 16550A > serial8250: ttyS1 at I/O 0x2f8 (irq = 3) is a 16550A > ttyS2: detected caps 00000700 should be 00000100 > 0000:01:00.0: ttyS2 at MMIO 0xdf601000 (irq = 16) is a 16C950/954 > ttyS3: detected caps 00000700 should be 00000100 > 0000:01:00.0: ttyS3 at MMIO 0xdf601200 (irq = 16) is a 16C950/954 > [root@mohon_peak ~]# > > Kyösti, I agree with you concerning the A9h post code. IMHO, I think it is > issued by the Intel FSP. > > BTW, > compiler complains about a mismatch argument type on read8() and write8() in > ./src/drivers/uart/uart8250mem.c Ah.. there is a recent regression with source. With complain like that it will not build you a new firmware binary at all, so it makes me wonder what you were actually testing before. Here is quick (but untested) fix for the build problem: http://review.coreboot.org/#/c/8660/ For a test run, I would need to disassemble a samsung/lumpy that I know OxPCIe works well with. That won't happen for at least a week. Kyösti -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
