Hello Werner, Could be that you are correct. I know that INTEL PED team themselves up-streamed the whole BDW-DE Coreboot code into Coreboot. Here is the pointer proving that: https://www.coreboot.org/pipermail/coreboot-gerrit/2016-April/042490.html
+config CPU_MICROCODE_HEADER_FILES + string + default "../intel/cpu/broadwell_de/microcode/M1050663_07000001.h ../intel/cpu/broadwell_de/microcode/M1050662_0000000A.h ../intel/cpu/broadwell_de/microcode/MFF50661_F1000008.h" The same I found in Jim's Coreboot config files: # CONFIG_BUILD_WITH_FAKE_IFD is not set CONFIG_TTYS0_BASE=0x3f8 CONFIG_CPU_MICROCODE_HEADER_FILES="../intel/cpu/broadwell_de/microcode/M1050663_07000001.h ../intel/cpu/broadwell_de/microcode/M1050662_0000000A.h ../intel/cpu/broadwell_de/microcode/MFF50661_F1000008.h" CONFIG_FSP_LOC=0xffeb0000 CONFIG_SOC_INTEL_FSP_BROADWELL_DE=y York (Yang) is the one who can precisely answer on these questions. and maybe provide the latest MCUs, or at least these could be used for googlthe more recent BDX-DE MCUs. Also, BDX-DE CPUID is important (I think for CPUIDs 0x50661, 0x50662, 0x50663 and assuming also 0x50664), so for different CPUIDs different MCU updates should be used (not 100% sure, thought). Best Regards, Zoran On Mon, Jul 4, 2016 at 12:39 PM, Zeh, Werner <[email protected]> wrote: > Hi Jim. > > > > According to the Postcode it seems like you have no valid microcode for > the used CPU. > > In src/drivers/intel/fsp1_0/cache_as_ram.inc is the code which ends up in > the endless loop while this code is shown. > > > > Check which CPU you really use on your mainboard and add the right > microcode to you configuration. > > This should solve your issue. > > > > Werner > > > > *Von:* coreboot [mailto:[email protected]] *Im Auftrag von * > ??? > *Gesendet:* Freitag, 1. Juli 2016 05:46 > *An:* [email protected] > *Betreff:* [coreboot] Bring up Intel Camelback Mountain Board with > coreboot+FSP failed > > > > Dear Sir, > > > > I just clone the latest coreboot source code from GIT > <http://review.coreboot.org/p/coreboot> and FSP from Intel FSP website > <https://downloadcenter.intel.com/download/25701>. > > Using " make crossgcc-i386 CPU=4 " to setup the compilation environment. > > But the Camelback Mountain board could not bring up successfully, > > it always hang with POST CODE = *0xCE*. > > From the Intel FSP spec 1.0, it seems that system halt before loading FSP. > > Attached is my .config file, is there anyone hit the fail symptoms same as > me and any idea to solve it? > > > > Thanks a lot, > > Jim > > > > -- > coreboot mailing list: [email protected] > https://www.coreboot.org/mailman/listinfo/coreboot >
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