Hi Zoran, thanks for checking back. I’m still on the issue (next to some other things), but haven’t made any progress yet. I also opened up a case at Intel Premier Support and tried to follow their suggestions (Case 00053422).
Anyway, I know the post_codes.h file. It defines POST_FSP_TEMP_RAM_INIT (0x90) which is the post code shown by coreboot just before it calls TempRamInit. Then TempRamInit shows 0x52. Intel suggested that this is a microcode problem (i.e. the microcode doesn’t match the CPU stepping or platform), however, I’m pretty sure that this is not the case. At least I’ve taken a look at the CPUID signature (which is 0x406C4) and the microcode header signature (which is 0x406C4). I also compared the platform ID bits from MSR 0x17 (which are 000, i.e. 1 << 000 = 1) with the platform ID field of the microcode (which is also 1). The microcode update facilities are documented in Intel’s System Programming Guide (#325384). I’m currently checking if coreboot is able to update the microcode while still in bootblock. There is a call to intel_update_microcode_from_cbfs() in /src/soc/intel/braswell/bootblock/bootblock.c. Maybe, there is something sticking out… Regards, Alex Von: Zoran Stojsavljevic [mailto:zoran.stojsavlje...@gmail.com] Gesendet: Montag, 25. Juli 2016 22:08 An: Alexander Böcken Cc: coreboot@coreboot.org; york.y...@intel.com Betreff: Re: [coreboot] Microcode problem with Braswell CPU Hello Alex, It is awhile... Opportunity just did struck (suddenly/plotzlich), so I am back! While lurking around in Coreboot, trying to solve some "Mystery of digital Orga.ni.sms", I ran into very interesting file: ./src/include/console/post_codes.h Coreboot tree I am using: [zoran@localhost coreboot-09.06.2016]$ git describe<CR> 4.4-455-g538b324 Maybe, it is worth looking into it. You tell us? Zoran On Tue, May 3, 2016 at 10:28 AM, Alexander Böcken <alexander.boec...@junger-audio.com<mailto:alexander.boec...@junger-audio.com>> wrote: Hello Zoran, again, thanks for your clues to this problem. I don't think post code 0x52 is about memory configuration. The post code appears when I call TempRamInit which is supposed to enable Cache-as-RAM. Real memory is initialized at a later call to FspMemoryInit. coreboot supplies the location of the microcode and a cachable region to TempRamInit. Additionally, there are some settings that can be applied to the FSP image with Intel's Binary Configuration Tool. I don't know if these are used during TempRamInit, but I'll try and fiddle around with them. I agree, it would be helpful to have a list of post codes that can be output by FSP. Otherwise it's all speculation as what is wrong. Regards, Alex
-- coreboot mailing list: coreboot@coreboot.org https://www.coreboot.org/mailman/listinfo/coreboot
