Hi Alex It's workable, after remove enable_rom_caching(). but I don't know why cpu will be impacted by MTRR. Thank you for your sharing
2016-07-27 16:56 GMT+08:00 Alexander Böcken < alexander.boec...@junger-audio.com>: > Hi all, > > > > I made a discovery yesterday that somehow solves my initial problem: > > > > The function bootblock_cpu_init() > (/src/soc/intel/braswell/bootblock/bootblock.c) contains a call to > enable_rom_caching(). If I remove this call then TempRamInit returns > successfully and coreboot is able to call cache_as_ram_main(). Hence, > TempRamInit must have returned a valid (cache) memory range and I have a > stack now. > > > > I don’t yet understand the implications of this “fix”, nor how it relates > to TempRamInit. Maybe, someone from Intel can shed light on this. Meanwhile > I’m learning about memory type range registers (MTRRs) because they are > being accessed in enable_rom_caching(). > > > > Also, cheng, can you confirm that this works for you? > > > > Best regards, > > Alex >
-- coreboot mailing list: coreboot@coreboot.org https://www.coreboot.org/mailman/listinfo/coreboot
