On Sun, Mar 12, 2017 at 5:53 PM, Gert Menke <[email protected]> wrote: > Hi, > > Thanks for your quick reply! > > On 2017-03-12 13:08, Kyösti Mälkki wrote: > >> We'll likely need coreboot debug logs. You can get one for normal boot >> using the tool under utils/cbmem, that might help us already. To >> collect log from failing S3 resume you need to learn about usbdebug >> and possibly get some FT232H or beaglebone hardware. >> > > I'll attach the cbmem log, both for a clean boot and a boot that happens > instead of the expected resume. > > As indicated by the clean boot log, it's a failure to write MRC cache. Could be that our SPI flash routines have regressed or were never tested for a setup with 4Mib + 8MiB SPI flash parts installed. Or there may be some unwritten rule about CBFS size and the location of MRC cache.
Kyösti
-- coreboot mailing list: [email protected] https://www.coreboot.org/mailman/listinfo/coreboot
