I included the microcode updates but no luck. The PCI IDs seem to be correct for Mullins [Radeon R3 Graphics] ( http://pci-ids.ucw.cz/read/PC/1002). *There is no serial port in the Olive Hill Plus board*. *What are my options*? Also how do i use this tool in util/cbmem/ ? I am using the default SeaBios as the payload.
On Tue, Apr 25, 2017 at 3:15 AM, ron minnich <[email protected]> wrote: > unless you're dead certain you don't need them, include microcode updates. > did you hook up a serial port? > > On Mon, Apr 24, 2017 at 2:44 PM Idwer Vollering <[email protected]> wrote: > >> 2017-04-24 21:08 GMT+02:00 Nagabhushan Shastry <[email protected]>: >> > Hi, >> > >> > I am trying to bring up the AMD G series Olive hill plus mainboard with >> > coreboot. >> > >> > These are the options i have enabled in make menuconfig but I am not >> able >> > to see anything on the screen when i power on the board. >> > Could someone please let me know if I am missing something. >> > >> > • General / Use CMOS for configuration values = enable (CMOS defaults >> are >> > located in your boards directory src/mainboard/OEM/MODEL/cmos.default) >> > • General / Include the coreboot .config file into the ROM image >> > • General / Compress ramstage with LZMA >> > • Mainboard / Mainboard vendor = AMD >> > • Mainboard / Mainboard model = Olive Hill plus >> > • Mainboard / ROM chip size = 8 MB >> > • Chipset / Include CPU microcode in CBFS = Do not include microcode >> updates >> > (NOTE: you probably want to enable it on some systems) >> > • Chipset / Enable Hudson XHCI Controller >> > • Chipset / Add xhci firmware >> > • (3rdparty/blobs/southbridge/amd/avalon/xhci.bin) XHCI firmware path >> and >> > filename >> > (3rdparty/blobs/southbridge/amd/avalon/PSP/AmdPubKey.bin) AMD public >> Key >> > • Devices / Run VGA Option ROMs >> > • Devices / Add a VGA BIOS image >> > (3rdparty/blobs/northbridge/amd/00730F01/VBIOS.bin) VGA BIOS path and >> > filename >> > (1002,9850) VGA device PCI IDs >> >> These PCI IDs, are they correct? Is the VBIOS, which I don't know >> anything about, executed? You need to have a way to see console >> output, either using the board's serial port or - presuming the >> mainboard boots to linux - through the utility found in util/cbmem/ >> >> > • Display / Keep VESA framebuffer = disable (disable for text-mode >> graphics, >> > enable for coreboot vesa framebuffer) >> > • Generic Drivers / Serial port on SuperIO >> > • Generic Drivers / Support Intel PCI-e WiFi adapters >> > • Console / Squelch AP CPUs from early console. >> > • Console / Serial port console output >> > • Console / Use onboard VGA as primary video device >> > • Console / Send console output to a CBMEM buffer >> > • Console / Send POST codes to an external device >> > • Console / Send POST codes to an IO port >> > • System tables / [*] Generate an MP table >> > • System tables / [*] Generate a PIRQ table >> > • System tables / [*] Generate SMBIOS tables >> > • Payload / SeaBIOS version (1.10.2) ---> >> > • Payload / Use LZMA compression for payloads >> > >> > -- >> > coreboot mailing list: [email protected] >> > https://mail.coreboot.org/mailman/listinfo/coreboot >> >> -- >> coreboot mailing list: [email protected] >> https://mail.coreboot.org/mailman/listinfo/coreboot > > > -- > coreboot mailing list: [email protected] > https://mail.coreboot.org/mailman/listinfo/coreboot >
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