Hi Cameron, Checked the postcodes and yes, last code is 0x93. And from the debug I noticed there are a lot of *"CBFS: Unmatched xxxxx"* print out. Do you get similar outputs from yours?
BTW, still wondering I was using the correct binaries in my config or not. What about yours settings for these ... :- CONFIG_VGA_BIOS_ID="1106,3230" (how to know and confirm this is my ID? is this important?) CONFIG_VGA_BIOS_FILE="3rdparty/blobs/mainboard/intel/apollolake_rvp/Vbt.bsf" (I have Vbt.bin and Vbt.bsf downloaded from Intel FSP_MR3, am I pionting to the correct one?) CONFIG_FMDFILE="src/mainboard/intel/leafhill/leafhill.$(CONFIG_COREBOOT_ROMSIZE_KB).fmd" (OK to use fmd from leafhill?) CONFIG_INTEL_GMA_VBT_FILE="3rdparty/blobs/mainboard/intel/ap ollolake_rvp/Vbt.bin" CONFIG_CHECKLIST_DATA_FILE_LOCATION="src/vendorcode/intel/fsp/fsp2_0/checklist" (I actually didn't see this file exist, is this important?) Thank you. - ahwan On Mon, Nov 6, 2017 at 10:45 PM, Cameron Craig <[email protected]> wrote: > Hi Ahwan, > > >coreboot-4.6-1941-g383ef6e-dirty Wed Nov 1 21:59:08 UTC 2017 ramstage > >starting... > >BS: BS_PRE_DEVICE times (us): entry 2 run 2 exit 0 > >FMAP: Found "FLASH" version 1.1 at 300000. > >FMAP: base = 0 size = 1000000 #areas = 11 > >FMAP: area COREBOOT found @ 300800 (12179456 bytes) CBFS @ 300800 size > >b9d800 > >CBFS: 'IAFW Locator' located CBFS at [300800:e9e000) > >CBFS: Locating 'fsps.bin' > >CBFS: Found @ offset 717c0 size 2a000 > >FMAP: area COREBOOT found @ 300800 (12179456 bytes) CBFS @ 300800 size > >b9d800 > >CBFS: 'IAFW Locator' located CBFS at [300800:e9e000) > >CBFS: Locating 'vbt.bin' > >CBFS: Found @ offset 9b800 size 1a00 > > > > > >I think I totally lost :( > >please let me know if you have any idea on how I can debug further. > >Thank you. > > > >-ahwan > > To me this looks like the FspSiliconInit() hang that a few of us are > experiencing with the ApolloLake FSP MR3. > > This has been raised with Intel. In the meantime I'm trying to get my > hands on the MR2 FSP (which should just work) through my Intel rep. > > You could turn on postcodes in the coreboot menuconfig, and if the last > postcode is 0x93 (about to call FspSiliconInit()), then you might have the > same problem. > > Cheers, > Cameron > > > > > Cameron Craig | Graduate Software Engineer | Exterity Limited > tel: +44 1383 828 250 | fax: | mobile: > e: [email protected] | w: www.exterity.com > > > > ______________________________________________________________________ > This email has been scanned by the Symantec Email Security.cloud service. > For more information please visit http://www.symanteccloud.com > ______________________________________________________________________ >
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