Hello Garrett, On 11.12.2017 18:16, GARRETT DOORENBOS wrote: > I'm running coreboot on an Intel Atom Bay Trail based platform. When I > turn off the CONFIG_ENABLE_FSP_FAST_BOOT flag, I get stuck in the Intel > FSP (it never returns) after a warm boot. The only way around it is a > power cycle. Has anyone seen this before?
AFAICS, the Bay Trail FSP doesn't have such an option. So it might be the case that the binary always expects a non-volative cache. But that is disabled in coreboot if you disable ENABLE_FSP_FAST_BOOT (by chance). Intel is known to present options where only one value works. The correct solution seems to be to always `select ENABLE_MRC_CACHE` for fsp_baytrail and remove the related guards in its code. And hide ENABLE_FSP_FAST_BOOT for fsp_baytrail because it just doesn't apply. May I ask why you want to disable fast boot? Hope that helps, Nico > Hello, > > > Thanks, > Garrett Doorenbos > Software Engineer - Almost Hardware > > Office: 256.963.6369 > Email: [email protected]<mailto:[email protected]> > Web: www.adtran.com<http://s.bl-1.com/h/CoY1mz9?url=http://www.adtran.com> > > ADTRAN > 901 Explorer Boulevard > Huntsville, AL 35806 - USA > > [ADTRAN]<http://s.bl-1.com/h/CoY1mz9?url=http://www.adtran.com> > -- coreboot mailing list: [email protected] https://mail.coreboot.org/mailman/listinfo/coreboot
