Hi, In case of Harcuvar CRB we have 16M SPI flash: first 8M for ME (which is outside of CBFS) and last 8M for coreboot. We need to specify two things in coreboot config:
- ROM chip size – 16M – physical size of SPI flash (needed for correct flash offset calculations inside coreboot code) - Size of CBFS filesystem in ROM – 8M (0x800000) or less 16M coreboot.rom file should be built with above config. You need to manually inject 8M ME blob at offset 0 into ‘coreboot.rom’ file. Or just flash last 8M from coreboot.rom into last 8M of SPI flash if ME blob is already there. Mariusz From: coreboot [mailto:coreboot-boun...@coreboot.org] On Behalf Of Sumo Sent: Monday, February 26, 2018 9:15 PM To: coreboot@coreboot.org Subject: [coreboot] Atom c3000 Harcuvar and Intel ME Hi, In the coreboot build menu there is no option regarding the Intel ME integration. The 'coreboot.rom' file is the full SPI flash image or this file is suitable to replace the BIOS region of the SPI flash (0x00800000--0x00ffffff)? (i.e. in the SPI flash we already have a region for Intel ME firmware) Thanks, Sumo -------------------------------------------------------------- Intel Research and Development Ireland Limited Registered in Ireland Registered Office: Collinstown Industrial Park, Leixlip, County Kildare Registered Number: 308263 This e-mail and any attachments may contain confidential material for the sole use of the intended recipient(s). Any review or distribution by others is strictly prohibited. If you are not the intended recipient, please contact the sender and delete all copies.
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