06.03.2018 09:55, Mark Wylde wrote: > I think I understand by your response that ASUS has used a 20 pin > connector on the motherboard part. Therefore they haven't connected up > the the ML1 lane. It also looks like with only 1 lane you can only have > a resolution of 1680×1050 (18 bit color depth)  which would be a > waste of the 15'' display. Although even if they did have the lane > exposes it looks like your helpful advice on the coreboot function would > be a bit out of my depth. > > So I think we can conclude it's impossible to get a bigger monitor (or > at least one with a bigger resolution) through the eDP port. I guess one > could get a controller board and hook the monitor up via the HDMI mini > port, but I think I'll pass on that. It was interesting to learn more > about eDP though.
The resolution isn't limited, only the data rate is. If the display supports different refresh rates than the usual 60Hz (possible, the datasheet isn't clear about that, IMHO), you can have a higher reso- lution at a lower refresh rate. So FHD at 50Hz might be possible with a single lane. You could try to figure the display's support for lower rates using the OS' driver (e.g. xrandr with Linux/X.Org). I'm not sure if the coreboot source is prepared for that, though. There are some pieces in the code that confuse me (e.g. the zeros passed to rk_edp_set_video_cr_mn(), Julius, do you happen to know something about that? is there public documentation for Rockchip's display engine?). I would, however, give the following one shot: 1. in soc/rockchip/common/edp.c line 615 override the lane count: edp->link_train.lane_count = 1; 2. in soc/rockchip/rk3288/display.c line 101 override the pixel clock: edid.mode.pixel_clock = 113850; The number assumes that the display can do 2.7GHz on the lane. You'd have to go down to 30Hz (68310) otherwise. Nico -- coreboot mailing list: email@example.com https://mail.coreboot.org/mailman/listinfo/coreboot