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On 05/17/2018 05:21 PM, Banik, Subrata wrote: Hi Subrata, > Can you please check few more things and please help to clarify > some details. > > 1. Is this kind of regression ? because we are not seeing this > issue. Can't tell that it is first time I try to enable Skylake in coreboot. > 2. I believe its FSP1.1 selection in Kconfig, please confirm ? FSP2.0, I'm following Librem Purism options since they seem to boot the same SoC. They use KabyLake FSP obtained by get_blobss.sh [1], if you think this is incorrect then I would like to know why, because it may mean that Pursim code is also incorrect from Intel point of view. > 3. Please check if BIOS_RESET_CPL is already set prior to setting > 0x121 MSR Refer to code enable_bios_reset_cpl Will do that and get back with result. > As per my debug MSR 0x121 will only through exception if BIOS > reset cpl done bits are already set before this call, which > shouldn't be the case, otherwise all SKL design might see this > issue. Would be great to know in which document I can read about this MSR. [1] https://github.com/osresearch/heads/blob/master/blobs/librem_skl/get_blo bs.sh Best Regards, - -- Piotr Król Embedded Systems Consultant https://3mdeb.com | @3mdeb_com -----BEGIN PGP SIGNATURE----- iQIzBAEBCAAdFiEE4DCbLYWmfoRjKeNLsu5x6WeqnkwFAlr9qOQACgkQsu5x6Weq nkzDFw//fb4JhiIszuDEbULkASGS9zJu++i+XWCeR2nhAaQIX8CAQYoHmxRV6nfW ANlZ7HYG/v1JSKMJEX7NuOXgdEK6atOKCEFRU5PH5PuXL74E3wlHQ+o4ivO8Myxa UE1jd7XaA7gMjMt5jMW4QMyjZPqdVHVAswp7qzdvied8Sxp1mqv1LNLeyI/uX/IS 6rbqSicMsknBuSqUPz6lKaFRBfQCOYnZ5UvsJLoh5CVglDnGBiPdOYjILbJXREJA 5xHlW9rTljukafmQE+FO5VDga8fDLQ435+uQEdZnVEtB2jWceSZTma9LCWX3AmYv A6Qt+5w/H/j7/1N55xH3jTR8Z/+QAdw3v3iGfr5vpVq/EMI89f+J16QyG5Y+SbNQ QFb4h/GRVan1WAS4cUjXMsCVSpg7b4mS7q2zjmMsG8DOp8jvywoa09179RYsEfIh PGAte6QnfpYP/TSgUM5AbhdIigwN/R1kAQPbrp5/M/AzljDwVCi2blOFLlkIcbED pjmnn+MJIz31wz6Jfb0D+umPmnPQz0HxUrg5sMAqXtVkyRgXH3Z9Av5pxtBbHwbD L6Y1qewQej4fpGSW8z4ozU+OnqhNk0/4ofp3D+YVP0zx+Vbu7dijGGdYG7G7VwhI 0YA7xUxucV+TYtPYg3pT3pFJz1shI8bNW6CtH6JpQarJhO9HMDQ= =HcYp -----END PGP SIGNATURE----- -- coreboot mailing list: [email protected] https://mail.coreboot.org/mailman/listinfo/coreboot
