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On 05/18/2018 07:53 PM, Youness Alaoui wrote: > Hi Piotr, Hi Youness, > Here's my librem13v2 info as reported by coreboot : CPU: Intel(R) > Core(TM) i7-6500U CPU @ 2.50GHz CPU: ID 406e3, Skylake D0, ucode: > 000000c1 CPU: AES supported, TXT NOT supported, VT supported MCH: > device id 1904 (rev 08) is Skylake-U PCH: device id 9d48 (rev 21) > is Skylake-U Premium IGD: device id 1916 (rev 07) is Skylake ULT > GT2 > > So I can see that we have the exact same CPU, MCH, PCH and IGD, > but there is one difference that I noticed, your line said : CPU: > ID 406e3, Skylake D0, ucode: 00000000 Good catch. I'm not sure why I can't include microcode that I obtained using get_blobs.sh. I marked: CONFIG_CPU_UCODE_BINARIES="cpu_microcode_blob.bin" But my results is: Name Offset Type Size Comp cbfs master header 0x0 cbfs header 32 none fallback/romstage 0x80 stage 47588 none fallback/ramstage 0xbb00 stage 84189 none vgaroms/seavgabios.bin 0x20440 raw 28672 none config 0x274c0 raw 457 none revision 0x27700 raw 580 none payload_revision 0x27980 raw 239 none (empty) 0x27ac0 null 1240 none fspm.bin 0x27fc0 fsp 389120 none payload_config 0x87000 raw 1682 none (empty) 0x87700 null 2200 none fsps.bin 0x87fc0 fsp 188416 none fallback/postcar 0xb6000 stage 31352 none fallback/dsdt.aml 0xbdac0 raw 12879 none fallback/payload 0xc0d80 simple elf 73920 none (empty) 0xd2e80 null 2877080 none cpu_microcode_blob.bin 0x391540 microcode 0 none (empty) 0x3915c0 null 1976792 none bootblock 0x573fc0 bootblock 49152 none So something wrong with size. I added microcode manually and things look better right now. Thank you. What is correct way to include binary microcode? In PC Engines we had to create our own method [1]. I wonder what would be correct way for tha t. [1] https://github.com/pcengines/coreboot/pull/132/files Best Regards, - -- Piotr Król Embedded Systems Consultant https://3mdeb.com | @3mdeb_com -----BEGIN PGP SIGNATURE----- iQIzBAEBCAAdFiEE4DCbLYWmfoRjKeNLsu5x6WeqnkwFAlsCA90ACgkQsu5x6Weq nkwJGQ//e5ujrAgQUyV97vEG92kz/nCv8qYKRAUUvjkeq2htz6RMy/FK74HxbOPM ITZvVc14ecWscpNyKCwWeWSAkf9UIxYR4MdN5D7CVsxP1/V3+H0uKi9JbrjPa4qe RVbPTpZC0vvadQ797KbVbj/i/i9B1j06LugAMF+utU0bB8oTb0bl2fliD62G7jbp JJTgX0cXyVQdfKV8593Wiy2lsrIi7nev701Yynpx4Qap+DBMLfQqFB6QEcCVopH0 gNIMnLgkK8PKlwfgj4+puAWnObpKkzaXZY1avoxCVzFllYF9Z9UoiNB8ZFjFEJ6P GkfNe/gxw8Rnh09eZH2z4peE2Ja0MFiBqyfbyiKMj7f1VYK+qEDhBZoV7NM2agZR iExXCINvLvBu8WTkaJ83dKjQwZ+NHqpfngqwdwW9kthMyHLyt0amSyYaJbsHJhAQ CDHaXCNFjvFA7BFSKiBuG4FLc+XMHEFSxP3EGfcWq3aPZ2LmjS/GrwRRHYjDvbBR JxNkppaWXrPRJ7XOmy94g9gL4hmcWD3QX40lqRGyQt0ZWDpG0FgjsoX6GBxhGSCL LH3SGTwYoXKGqUp39YaPPACq0nJtxkTtCMK+ZH0D9Q173lngGewc5BtASgQIGWl6 UW6G8A/EmDmpCFA3xe3Rlj+PWm46w3cBWEizx4pPSYoycMYlSBk= =mfsi -----END PGP SIGNATURE----- -- coreboot mailing list: coreboot@coreboot.org https://mail.coreboot.org/mailman/listinfo/coreboot