Hi,
We are developing coreboot (with Intel FSP) for apollo lake platform custom
board. We are facing a hang issue during the SYS_RESET button press.
Observations:
* With soft reset the board gets hang(occurs within 2 or 3 reboot) with
POST code 0x38 and the coreboot log stops during the romstage relocation. (Logs
attached for Ref.)
* When the SYS_RESET is pressed again the board boots and hangs at same
POST code 0x38.
Please provide feedback and help us to resolve this issue.
Currently our coreboot build does not include any microcode
(CPU_MICROCODE_CBFS_NONE). We tried to change it as "Generate from tree" in
memuconfig.
But the build fails with fatal error saying no microcode/microcode.h file.
Whether the CPU by default have microcode ? or we need to build the microcode
in coreboot ?
Please advise on this.
Thanks & Regards,
Antony
L&T Technology Services Ltd
www.LntTechservices.com<http://www.lnttechservices.com/>
This Email may contain confidential or privileged information for the intended
recipient (s). If you are not the intended recipient, please do not use or
disseminate the information, notify the sender and delete it from your system.
coreboot-APOLLOLAKE_CB_MR4_001 Wed Nov 7 09:44:01 UTC 2018 verstage starting...
FSP TempRamInit successful
0xfef15ff0: fsp_boot_context
0x0000000035249773: tsc
0xffffdc94: fih
0x00000000: bist
0x5aa55aa5: hash
FSP_INFO_HEADER: ffffdc94
FSP Signature: $APLFSP$
FSP Header Version: 3
FSP Revision: 1.4.3.1
Entering cbfs_boot_locate
Entering boot_device_init in boot_device.c
CBFS @ 0 size 7c40
CBFS: Locating 'verstage.rel'
CBFS: Found @ offset 1f00 size 14c
verstage is relocated from ffff8054 to 0xfef07054
CPU: frequency set to 1300 MHz
Entering asset_locate
Entering boot_device_init in boot_device.c
CBFS provider active.
Entering cbfs_boot_locate
Entering boot_device_init in boot_device.c
CBFS @ 0 size 70000
CBFS: Locating 'fallback/romstage'
CBFS: Found @ offset 0 size 6488
'fallback/romstage' located at offset: 38 size: 6488
CSE IBB verification result: 1
ID:18 Time:1739923Entering cbfs_boot_locate
Entering boot_device_init in boot_device.c
CBFS @ 0 size 70000
CBFS: Locating 'fsp.bin'
CBFS: Found @ offset 16ec0 size 59000
ID:1 Time:2260521817
coreboot-APOLLOLAKE_CB_MR4_001 Wed Nov 7 09:44:01 UTC 2018 romstage starting...
bist: 0x00000000
tsc_low: 0x00000000
tsc_hi: 0x00000000
CONFIG_MMCONF_BASE_ADDRESS: 0xe0000000
Using: FSP 2.0
FSP_INFO_HEADER: fef56f94
FSP Signature: $APLFSP$
FSP Header Version: 3
FSP Revision: 1.4.3.1
PM1_STS: 0000
PM1_EN: 0000
PM1_CNT: 00000000
TCO_STS: 0000 0000
GPE0_STS: 00000000 00000000 00000000 00000000
GPE0_EN: 00000000 00000000 00000000 00000000
Previous Sleep State: S0
CPU: Intel(R) Atom(TM) Processor E3930 @ 1.30GHz
CPU: ID 506c9, Apollolake B0, ucode: 00000026
CPU: AES supported, TXT NOT supported, VT supported
CPU: frequency set to 1300 MHz
ID:2 Time:2348925702WEAK: src/soc/intel/common/romstage.c/mrc_cache_get_current
called
No MRC cache found.
WEAK: src/soc/intel/common/romstage.c/mainboard_check_ec_image called
UPD Data: 0xfef57024
PreMemGpioTablePtr: 0x0
Calling FspMemoryInit: 0xfef572f8
0x00000000: NvsBufferPtr
0xfef1546c: FspmConfig
0xfef153f0: HobListPtr
ID:950 Time:2392607544ID:951 Time:#^!3935713053FspMemoryInit returned 0x00000000
Reserving 0x0000000000400000 bytes from 0x000000007abfe000 for FSP
0x00800000: smm_size
0x7b000000: smm_base
0x7b000000: cbmem_top
CBMEM:
IMD: root @ 7afff000 254 entries.
IMD: root @ 7affec00 62 entries.
smm_subregion:1, start=0x7b700000, size=0x100000
External stage cache:
IMD: root @ 7b7ff000 254 entries.
IMD: root @ 7b7fec00 62 entries.
0x7abfe000: fsp_reserved_memory_area
ID:3 Time:#^!3992553553MRC data at 7ac1f0d0 45792 bytes
WEAK: src/soc/intel/common/romstage.c/mrc_cache_stash_data called
CBMEM entry for DIMM info: 0x7affe8c0
1 DIMMs found
WEAK: src/soc/intel/common/romstage.c/soc_after_ram_init called
Calling FspTempRamExit API
ID:952 Time:#^!4026754805Entering cbfs_boot_locate
Entering boot_device_init in boot_device.c
CBFS @ 0 size 70000
CBFS: Locating 'romstage.rel'
CBFS: Found @ offset 64c0 size 480
romstage is relocated from fef40054 to 0x7abf1000
ID:953 Time:#^!2174716835FspTempRamExit returned successfully
WEAK: src/soc/intel/common/romstage.c/soc_after_temp_ram_exit called
S3 status: 0
Adding obb_reserved_memory_area = 0x7a9f0000
Entering cbfs_boot_locate
Entering boot_device_init in boot_device.c
CBFS @ 0 size 1ffc40
CBFS: Locating 'fsp.bin'
CBFS: Found @ offset 500 size 2a000
FSP_INFO_HEADER: 7a9f05cc
FSP Signature: $APLFSP$
FSP Header Version: 3
FSP Revision: 1.4.3.1
ID:4 Time:#^!2232671745Entering asset_locate
Entering boot_device_init in boot_device.c
CBFS provider active.
Entering cbfs_boot_locate
Entering boot_device_init in boot_device.c
CBFS @ 0 size 1ffc40
CBFS: Locating 'fallback/ramstage'
CBFS: Found @ offset 2a540 size 15065
'fallback/ramstage' located at offset: 2a578 size: 15065
ID:8 Time:#^!2275244577Decompressing stage fallback/ramstage @ 0x7a926fc0
(822400 bytes)
ID:15 Time:#^!2286532406ID:16 Time:#^!2337049202Loading module at 7a927000 with
entry 7a927000. filesize: 0x369f0 memsize: 0xc8c40
Processing 11971 relocs. Offset value of 0x7a927000
ID:9 Time:#^!2387438432
coreboot-APOLLOLAKE_CB_MR4_001 Wed Nov 7 09:44:01 UTC 2018 ramstage starting...
smm_subregion:1, start=0x7b700000, size=0x100000
Moving GDT to 7affe6a0...ok
ID:10 Time:#^!2411164955BS: BS_PRE_DEVICE times (us): entry 0 run 4 exit 0
ID:30 Time:#^!2420719486Entering cbfs_boot_locate
Entering boot_device_init in boot_device.c
CBFS @ 0 size 1ffc40
CBFS: Locating 'fsp.bin'
CBFS: Found @ offset 500 size 2a000
FSP: Saving binary in cache
FSP_INFO_HEADER: 7a8fc094
FSP Signature: $APLFSP$
FSP Header Version: 3
FSP Revision: 1.4.3.1
UPD Data: 0x7a8fc124
Calling FspSiliconInit
Calling FspSiliconInit(0x7a961b60) at 0x7a8fc5b2
ID:954 Time:#^!2485574936ID:955 Time:#^!3151033741FspSiliconInit returned
0x00000000
src/soc/intel/apllake/ramstage.c/soc_after_silicon_init called
Hiding P2SB before bus enumerate so P2SB bar will not be re-written
BS: BS_DEV_INIT_CHIPS times (us): entry 0 run 586671 exit 0
Enumerating buses...
Show all devs... Before device enumeration.
Root Device: enabled 1
CPU_CLUSTER: 0: enabled 1
APIC: 00: enabled 1
DOMAIN: 0000: enabled 1
PCI: 00:00.0: enabled 1
PCI: 00:0d.0: enabled 1
PCI: 00:0d.1: enabled 1
PCI: 00:0d.2: enabled 1
PCI: 00:0d.3: enabled 1
PCI: 00:11.0: enabled 1
PCI: 00:15.0: enabled 1
PCI: 00:13.0: enabled 1
PCI: 00:13.1: enabled 1
PCI: 00:18.1: enabled 1
PCI: 00:18.2: enabled 1
PCI: 00:1f.0: enabled 1
PCI: 00:1f.1: enabled 1
Compare with tree...
Root Device: enabled 1
CPU_CLUSTER: 0: enabled 1
APIC: 00: enabled 1
DOMAIN: 0000: enabled 1
PCI: 00:00.0: enabled 1
PCI: 00:0d.0: enabled 1
PCI: 00:0d.1: enabled 1
PCI: 00:0d.2: enabled 1
PCI: 00:0d.3: enabled 1
PCI: 00:11.0: enabled 1
PCI: 00:15.0: enabled 1
PCI: 00:13.0: enabled 1
PCI: 00:13.1: enabled 1
PCI: 00:18.1: enabled 1
PCI: 00:18.2: enabled 1
PCI: 00:1f.0: enabled 1
PCI: 00:1f.1: enabled 1
Root Device scanning...
root_dev_scan_bus for Root Device
CPU_CLUSTER: 0 enabled
DOMAIN: 0000 enabled
DOMAIN: 0000 scanning...
PCI: pci_scan_bus for bus 00
PCI: 00:00.0 [8086/0000] ops
PCI: 00:00.0 [8086/5af0] enabled
PCI: 00:00.1 [8086/5a8c] enabled
PCI: 00:02.0 [8086/5a85] enabled
PCI: Static device PCI: 00:0d.0 not found, disabling it.
PCI: 00:0d.1 [8086/5a94] enabled
PCI: 00:0d.2 [8086/5a96] enabled
PCI: 00:0d.3 [8086/5aec] enabled
PCI: 00:0f.0 [8086/5a9a] enabled
PCI: 00:0f.1 [8086/5a9c] enabled
PCI: 00:0f.2 [8086/5a9e] enabled
PCI: Static device PCI: 00:11.0 not found, disabling it.
PCI: 00:13.0 [8086/0000] bus ops
PCI: 00:13.0 [8086/5ad8] enabled
PCI: 00:13.1 [8086/0000] bus ops
PCI: 00:13.1 [8086/5ad9] enabled
PCI: 00:15.0 [8086/5aa8] enabled
PCI: 00:1f.0 [8086/0000] bus ops
PCI: 00:1f.0 [8086/5ae8] enabled
PCI: 00:1f.1 [8086/0000] bus ops
PCI: 00:1f.1 [8086/5ad4] enabled
PCI: Left over static devices:
PCI: 00:18.1
PCI: 00:18.2
PCI: Check your devicetree.cb.
PCI: 00:13.0 scanning...
do_pci_scan_bridge for PCI: 00:13.0
PCI: pci_scan_bus for bus 01
PCI: 00:13.1 scanning...
do_pci_scan_bridge for PCI: 00:13.1
PCI: pci_scan_bus for bus 02
PCI: 00:1f.0 scanning...
scan_lpc_bus for PCI: 00:1f.0
scan_lpc_bus for PCI: 00:1f.0 done
PCI: 00:1f.1 scanning...
scan_smbus for PCI: 00:1f.1
scan_smbus for PCI: 00:1f.1 done
root_dev_scan_bus for Root Device done
done
BS: BS_DEV_ENUMERATE times (us): entry 0 run 4290515172 exit 0
ID:40 Time:#^!3492675175Allocating resources...
Reading resources...
Root Device read_resources bus 0 link: 0
CPU_CLUSTER: 0 missing read_resources
DOMAIN: 0000 read_resources bus 0 link: 0
PCI: 00:13.0 read_resources bus 1 link: 0
PCI: 00:13.0 read_resources bus 1 link: 0 done
PCI: 00:13.1 read_resources bus 2 link: 0
PCI: 00:13.1 read_resources bus 2 link: 0 done
DOMAIN: 0000 read_resources bus 0 link: 0 done
Root Device read_resources bus 0 link: 0 done
Done reading resources.
coreboot-APOLLOLAKE_CB_MR4_001 Wed Nov 7 09:44:01 UTC 2018 verstage starting...
FSP TempRamInit successful
0xfef15ff0: fsp_boot_context
0x0000000033a0c678: tsc
0xffffdc94: fih
0x00000000: bist
0x5aa55aa5: hash
FSP_INFO_HEADER: ffffdc94
FSP Signature: $APLFSP$
FSP Header Version: 3
FSP Revision: 1.4.3.1
Entering cbfs_boot_locate
Entering boot_device_init in boot_device.c
CBFS @ 0 size 7c40
CBFS: Locating 'verstage.rel'
CBFS: Found @ offset 1f00 size 14c
verstage is relocated from ffff8054 to 0xfef07054
CPU: frequency set to 1300 MHz
Entering asset_locate
Entering boot_device_init in boot_device.c
CBFS provider active.
Entering cbfs_boot_locate
Entering boot_device_init in boot_device.c
CBFS @ 0 size 70000
CBFS: Locating 'fallback/romstage'
CBFS: Found @ offset 0 size 6488
'fallback/romstage' located at offset: 38 size: 6488
CSE IBB verification result: 1
ID:18 Time:1766634Entering cbfs_boot_locate
Entering boot_device_init in boot_device.c
CBFS @ 0 size 70000
CBFS: Locating 'fsp.bin'
CBFS: Found @ offset 16ec0 size 59000
ID:1 Time:2294885364
coreboot-APOLLOLAKE_CB_MR4_001 Wed Nov 7 09:44:01 UTC 2018 romstage starting...
bist: 0x00000000
tsc_low: 0x00000000
tsc_hi: 0x00000000
CONFIG_MMCONF_BASE_ADDRESS: 0xe0000000
Using: FSP 2.0
FSP_INFO_HEADER: fef56f94
FSP Signature: $APLFSP$
FSP Header Version: 3
FSP Revision: 1.4.3.1
PM1_STS: 0000
PM1_EN: 0000
PM1_CNT: 00000000
TCO_STS: 0000 0000
GPE0_STS: 00000000 00000000 00000000 00000000
GPE0_EN: 00000000 00000000 00000000 00000000
Previous Sleep State: S0
CPU: Intel(R) Atom(TM) Processor E3930 @ 1.30GHz
CPU: ID 506c9, Apollolake B0, ucode: 00000026
CPU: AES supported, TXT NOT supported, VT supported
CPU: frequency set to 1300 MHz
ID:2 Time:2383290865WEAK: src/soc/intel/common/romstage.c/mrc_cache_get_current
called
No MRC cache found.
WEAK: src/soc/intel/common/romstage.c/mainboard_check_ec_image called
UPD Data: 0xfef57024
PreMemGpioTablePtr: 0x0
Calling FspMemoryInit: 0xfef572f8
0x00000000: NvsBufferPtr
0xfef1546c: FspmConfig
0xfef153f0: HobListPtr
ID:950 Time:2426975730ID:951 Time:2651627365FspMemoryInit returned 0x00000000
Reserving 0x0000000000400000 bytes from 0x000000007abfe000 for FSP
0x00800000: smm_size
0x7b000000: smm_base
0x7b000000: cbmem_top
CBMEM:
IMD: root @ 7afff000 254 entries.
IMD: root @ 7affec00 62 entries.
smm_subregion:1, start=0x7b700000, size=0x100000
External stage cache:
IMD: root @ 7b7ff000 254 entries.
IMD: root @ 7b7fec00 62 entries.
0x7abfe000: fsp_reserved_memory_area
ID:3 Time:2708068813MRC data at 7ac1f0d0 45792 bytes
WEAK: src/soc/intel/common/romstage.c/mrc_cache_stash_data called
CBMEM entry for DIMM info: 0x7affe8c0
1 DIMMs found
WEAK: src/soc/intel/common/romstage.c/soc_after_ram_init called
Calling FspTempRamExit API
ID:952 Time:2741745790Entering cbfs_boot_locate
Entering boot_device_init in boot_device.c
CBFS @ 0 size 70000
CBFS: Locating 'romstage.rel'
CBFS: Found @ offset 64c0 size 480
romstage is relocated from fef40054 to 0x7abf1000
ID:953 Time:#^!234044777FspTempRamExit returned successfully
WEAK: src/soc/intel/common/romstage.c/soc_after_temp_ram_exit called
S3 status: 0
Adding obb_reserved_memory_area = 0x7a9f0000
Entering cbfs_boot_locate
Entering boot_device_init in boot_device.c
CBFS @ 0 size 1ffc40
CBFS: Locating 'fsp.bin'
CBFS: Found @ offset 500 size 2a000
FSP_INFO_HEADER: 7a9f05cc
FSP Signature: $APLFSP$
FSP Header Version: 3
FSP Revision: 1.4.3.1
ID:4 Time:#^!291448992Entering asset_locate
Entering boot_device_init in boot_device.c
CBFS provider active.
Entering cbfs_boot_locate
Entering boot_device_init in boot_device.c
CBFS @ 0 size 1ffc40
CBFS: Locating 'fallback/ramstage'
CBFS: Found @ offset 2a540 size 15065
'fallback/ramstage' located at offset: 2a578 size: 15065
ID:8 Time:#^!333853688Decompressing stage fallback/ramstage @ 0x7a926fc0
(822400 bytes)
ID:15 Time:#^!345021820ID:16 Time:#^!395392083Loading module at 7a927000 with
entry 7a927000. filesize: 0x369f0 memsize: 0xc8c40
Processing 11971 relocs. Offset value of 0x7a927000
ID:9 Time:#^!445644497
coreboot-APOLLOLAKE_CB_MR4_001 Wed Nov 7 09:44:01 UTC 2018 ramstage starting...
smm_subregion:1, start=0x7b700000, size=0x100000
Moving GDT to 7affe6a0...ok
ID:10 Time:#^!469160269BS: BS_PRE_DEVICE times (us): entry 1 run 3 exit 1
ID:30 Time:#^!478592135Entering cbfs_boot_locate
Entering boot_device_init in boot_device.c
CBFS @ 0 size 1ffc40
CBFS: Locating 'fsp.bin'
CBFS: Found @ offset 500 size 2a000
FSP: Saving binary in cache
FSP_INFO_HEADER: 7a8fc094
FSP Signature: $APLFSP$
FSP Header Version: 3
FSP Revision: 1.4.3.1
UPD Data: 0x7a8fc124
Calling FspSiliconInit
Calling FspSiliconInit(0x7a961b60) at 0x7a8fc5b2
ID:954 Time:#^!540304572ID:955 Time:#^!761110170FspSiliconInit returned
0x00000000
src/soc/intel/apllake/ramstage.c/soc_after_silicon_init called
Hiding P2SB before bus enumerate so P2SB bar will not be re-written
BS: BS_DEV_INIT_CHIPS times (us): entry 0 run 238526 exit 0
Enumerating buses...
Show all devs... Before device enumeration.
Root Device: enabled 1
CPU_CLUSTER: 0: enabled 1
APIC: 00: enabled 1
DOMAIN: 0000: enabled 1
PCI: 00:00.0: enabled 1
PCI: 00:0d.0: enabled 1
PCI: 00:0d.1: enabled 1
PCI: 00:0d.2: enabled 1
PCI: 00:0d.3: enabled 1
PCI: 00:11.0: enabled 1
PCI: 00:15.0: enabled 1
PCI: 00:13.0: enabled 1
PCI: 00:13.1: enabled 1
PCI: 00:18.1: enabled 1
PCI: 00:18.2: enabled 1
PCI: 00:1f.0: enabled 1
PCI: 00:1f.1: enabled 1
Compare with tree...
Root Device: enabled 1
CPU_CLUSTER: 0: enabled 1
APIC: 00: enabled 1
DOMAIN: 0000: enabled 1
PCI: 00:00.0: enabled 1
PCI: 00:0d.0: enabled 1
PCI: 00:0d.1: enabled 1
PCI: 00:0d.2: enabled 1
PCI: 00:0d.3: enabled 1
PCI: 00:11.0: enabled 1
PCI: 00:15.0: enabled 1
PCI: 00:13.0: enabled 1
PCI: 00:13.1: enabled 1
PCI: 00:18.1: enabled 1
PCI: 00:18.2: enabled 1
PCI: 00:1f.0: enabled 1
PCI: 00:1f.1: enabled 1
Root Device scanning...
root_dev_scan_bus for Root Device
CPU_CLUSTER: 0 enabled
DOMAIN: 0000 enabled
DOMAIN: 0000 scanning...
PCI: pci_scan_bus for bus 00
PCI: 00:00.0 [8086/0000] ops
PCI: 00:00.0 [8086/5af0] enabled
PCI: 00:00.1 [8086/5a8c] enabled
PCI: 00:02.0 [8086/5a85] enabled
PCI: Static device PCI: 00:0d.0 not found, disabling it.
PCI: 00:0d.1 [8086/5a94] enabled
PCI: 00:0d.2 [8086/5a96] enabled
PCI: 00:0d.3 [8086/5aec] enabled
PCI: 00:0f.0 [8086/5a9a] enabled
PCI: 00:0f.1 [8086/5a9c] enabled
PCI: 00:0f.2 [8086/5a9e] enabled
PCI: Static device PCI: 00:11.0 not found, disabling it.
PCI: 00:13.0 [8086/0000] bus ops
PCI: 00:13.0 [8086/5ad8] enabled
PCI: 00:13.1 [8086/0000] bus ops
PCI: 00:13.1 [8086/5ad9] enabled
PCI: 00:15.0 [8086/5aa8] enabled
PCI: 00:1f.0 [8086/0000] bus ops
PCI: 00:1f.0 [8086/5ae8] enabled
PCI: 00:1f.1 [8086/0000] bus ops
PCI: 00:1f.1 [8086/5ad4] enabled
PCI: Left over static devices:
PCI: 00:18.1
PCI: 00:18.2
PCI: Check your devicetree.cb.
PCI: 00:13.0 scanning...
do_pci_scan_bridge for PCI: 00:13.0
PCI: pci_scan_bus for bus 01
PCI: 00:13.1 scanning...
do_pci_scan_bridge for PCI: 00:13.1
PCI: pci_scan_bus for bus 02
PCI: 00:1f.0 scanning...
scan_lpc_bus for PCI: 00:1f.0
scan_lpc_bus for PCI: 00:1f.0 done
PCI: 00:1f.1 scanning...
scan_smbus for PCI: 00:1f.1
scan_smbus for PCI: 00:1f.1 done
root_dev_scan_bus for Root Device done
done
BS: BS_DEV_ENUMERATE times (us): entry 0 run 234172 exit 0
ID:40 Time:#^!1101929758Allocating resources...
Reading resources...
Root Device read_resources bus 0 link: 0
CPU_CLUSTER: 0 missing read_resources
DOMAIN: 0000 read_resources bus 0 link: 0
PCI: 00:13.0 read_resources bus 1 link: 0
PCI: 00:13.0 read_resources bus 1 link: 0 done
PCI: 00:13.1 read_resources bus 2 link: 0
PCI: 00:13.1 read_resources bus 2 link: 0 done
DOMAIN: 0000 read_resources bus 0 link: 0 done
Root Device read_resources bus 0 link: 0 done
Done reading resources.
Show resources in subtree (Root Device)...After reading.
Root Device child on link 0 CPU_CLUSTER: 0
CPU_CLUSTER: 0 child on link 0 APIC: 00
APIC: 00
DOMAIN: 0000 child on link 0 PCI: 00:00.0
DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100
index 10000000
DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags
40040200 index 10000100
PCI: 00:00.0
PCI: 00:00.0 resource base 0 size a0000 align 0 gran 0 limit 0 flags
e0004200 index 0
PCI: 00:00.0 resource base a0000 size 20000 align 0 gran 0 limit 0 flags
f0000200 index 1
PCI: 00:00.0 resource base c0000 size 40000 align 0 gran 0 limit 0 flags
f0004200 index 2
PCI: 00:00.0 resource base 7b000000 size 800000 align 0 gran 0 limit 0 flags
f0004200 index 3
PCI: 00:00.0 resource base 7b800000 size 4800000 align 0 gran 0 limit 0
flags f0004200 index 4
PCI: 00:00.0 resource base 7affe000 size 2000 align 0 gran 0 limit 0 flags
f0004200 index 5
PCI: 00:00.0 resource base 7abfe000 size 400000 align 0 gran 0 limit 0 flags
f0004200 index 6
PCI: 00:00.0 resource base 100000 size ff00000 align 0 gran 0 limit 0 flags
e0004200 index 7
PCI: 00:00.0 resource base 10000000 size 2151000 align 0 gran 0 limit 0
flags f0004200 index 8
PCI: 00:00.0 resource base 12151000 size 68aad000 align 0 gran 0 limit 0
flags e0004200 index 9
PCI: 00:00.0 resource base d0000000 size 10000000 align 0 gran 0 limit 0
flags f0000200 index a
PCI: 00:00.0 resource base fef00000 size 1000 align 0 gran 0 limit 0 flags
f0000200 index b
PCI: 00:00.0 resource base e0000000 size 10000000 align 0 gran 0 limit 0
flags f0000200 index c
PCI: 00:00.1
PCI: 00:00.1 resource base 0 size 8000 align 15 gran 15 limit #^!ffffffff
flags 201 index 10
PCI: 00:02.0
PCI: 00:02.0 resource base 0 size 1000000 align 24 gran 24 limit #^!ffffffff
flags 201 index 10
PCI: 00:02.0 resource base 0 size 10000000 align 28 gran 28 limit
#^!ffffffff flags 1201 index 18
PCI: 00:02.0 resource base 0 size 40 align 6 gran 6 limit ffff flags 100
index 20
PCI: 00:0d.0
PCI: 00:0d.1
PCI: 00:0d.1 resource base 0 size 2000 align 13 gran 13 limit #^!ffffffff
flags 201 index 10
PCI: 00:0d.1 resource base 0 size 1000 align 12 gran 12 limit #^!ffffffff
flags 201 index 18
PCI: 00:0d.2
PCI: 00:0d.2 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags
200 index 10
PCI: 00:0d.3
PCI: 00:0d.3 resource base 0 size 2000 align 13 gran 13 limit #^!ffffffff
flags 201 index 10
PCI: 00:0d.3 resource base 0 size 1000 align 12 gran 12 limit #^!ffffffff
flags 201 index 18
PCI: 00:0f.0
PCI: 00:0f.0 resource base 0 size 1000 align 12 gran 12 limit #^!ffffffff
flags 201 index 10
PCI: 00:0f.1
PCI: 00:0f.1 resource base 0 size 1000 align 12 gran 12 limit #^!ffffffff
flags 201 index 10
PCI: 00:0f.2
PCI: 00:0f.2 resource base 0 size 1000 align 12 gran 12 limit #^!ffffffff
flags 201 index 10
PCI: 00:11.0
PCI: 00:13.0
PCI: 00:13.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102
index 1c
PCI: 00:13.0 resource base 0 size 0 align 20 gran 20 limit #^!ffffffff flags
81202 index 24
PCI: 00:13.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags
80202 index 20
PCI: 00:13.1
PCI: 00:13.1 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102
index 1c
PCI: 00:13.1 resource base 0 size 0 align 20 gran 20 limit #^!ffffffff flags
81202 index 24
PCI: 00:13.1 resource base 0 size 0 align 20 gran 20 limit ffffffff flags
80202 index 20
PCI: 00:15.0
PCI: 00:15.0 resource base 0 size 10000 align 16 gran 16 limit #^!ffffffff
flags 201 index 10
PCI: 00:1f.0
PCI: 00:1f.0 resource base d0000000 size 30000000 align 0 gran 0 limit 0
flags d0000200 index 10
PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0000100
index 0
PCI: 00:1f.1
PCI: 00:1f.1 resource base efa0 size 20 align 0 gran 0 limit efbf flags
f0000100 index 20
PCI: 00:1f.1 resource base 0 size 100 align 8 gran 8 limit #^!ffffffff flags
201 index 10
DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff
PCI: 00:13.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff
PCI: 00:13.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done
PCI: 00:13.1 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff
PCI: 00:13.1 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done
PCI: 00:02.0 20 * [0x0 - 0x3f] io
DOMAIN: 0000 io: base: 40 size: 40 align: 6 gran: 0 limit: ffff done
DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff
PCI: 00:13.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: #^!ffffffff
PCI: 00:13.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: #^!ffffffff done
PCI: 00:13.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
PCI: 00:13.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done
PCI: 00:13.1 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: #^!ffffffff
PCI: 00:13.1 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: #^!ffffffff done
PCI: 00:13.1 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
PCI: 00:13.1 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done
PCI: 00:02.0 18 * [0x0 - 0xfffffff] prefmem
PCI: 00:02.0 10 * [0x10000000 - 0x10ffffff] mem
PCI: 00:15.0 10 * [0x11000000 - 0x1100ffff] mem
PCI: 00:00.1 10 * [0x11010000 - 0x11017fff] mem
PCI: 00:0d.1 10 * [0x11018000 - 0x11019fff] mem
PCI: 00:0d.3 10 * [0x1101a000 - 0x1101bfff] mem
PCI: 00:0d.1 18 * [0x1101c000 - 0x1101cfff] mem
PCI: 00:0d.2 10 * [0x1101d000 - 0x1101dfff] mem
PCI: 00:0d.3 18 * [0x1101e000 - 0x1101efff] mem
PCI: 00:0f.0 10 * [0x1101f000 - 0x1101ffff] mem
PCI: 00:0f.1 10 * [0x11020000 - 0x11020fff] mem
PCI: 00:0f.2 10 * [0x11021000 - 0x11021fff] mem
PCI: 00:1f.1 10 * [0x11022000 - 0x110220ff] mem
DOMAIN: 0000 mem: base: 11022100 size: 11022100 align: 28 gran: 0 limit:
ffffffff done
avoid_fixed_resources: DOMAIN: 0000
avoid_fixed_resources:@DOMAIN: 0000 10000000 limit 0000ffff
avoid_fixed_resources:@DOMAIN: 0000 10000100 limit ffffffff
constrain_resources: PCI: 00:00.0 00 base 00000000 limit 0009ffff mem (fixed)
constrain_resources: PCI: 00:00.0 01 base 000a0000 limit 000bffff mem (fixed)
constrain_resources: PCI: 00:00.0 02 base 000c0000 limit 000fffff mem (fixed)
constrain_resources: PCI: 00:00.0 03 base 7b000000 limit 7b7fffff mem (fixed)
constrain_resources: PCI: 00:00.0 04 base 7b800000 limit 7fffffff mem (fixed)
constrain_resources: PCI: 00:00.0 0a base d0000000 limit dfffffff mem (fixed)
constrain_resources: PCI: 00:1f.0 00 base 00000000 limit 00000fff io (fixed)
constrain_resources: PCI: 00:1f.1 20 base 0000efa0 limit 0000efbf io (fixed)
avoid_fixed_resources:@DOMAIN: 0000 10000000 base 00001000 limit 0000ef9f
avoid_fixed_resources:@DOMAIN: 0000 10000100 base b0000000 limit cfffffff
Setting resources...
DOMAIN: 0000 io: base:1000 size:40 align:6 gran:0 limit:ef9f
PCI: 00:02.0 20 * [0x1000 - 0x103f] io
DOMAIN: 0000 io: next_base: 1040 size: 40 align: 6 gran: 0 done
PCI: 00:13.0 io: base:ef9f size:0 align:12 gran:12 limit:ef9f
PCI: 00:13.0 io: next_base: ef9f size: 0 align: 12 gran: 12 done
PCI: 00:13.1 io: base:ef9f size:0 align:12 gran:12 limit:ef9f
PCI: 00:13.1 io: next_base: ef9f size: 0 align: 12 gran: 12 done
DOMAIN: 0000 mem: base:b0000000 size:11022100 align:28 gran:0 limit:cfffffff
PCI: 00:02.0 18 * [0xb0000000 - 0xbfffffff] prefmem
PCI: 00:02.0 10 * [0xc0000000 - 0xc0ffffff] mem
PCI: 00:15.0 10 * [0xc1000000 - 0xc100ffff] mem
PCI: 00:00.1 10 * [0xc1010000 - 0xc1017fff] mem
PCI: 00:0d.1 10 * [0xc1018000 - 0xc1019fff] mem
PCI: 00:0d.3 10 * [0xc101a000 - 0xc101bfff] mem
PCI: 00:0d.1 18 * [0xc101c000 - 0xc101cfff] mem
PCI: 00:0d.2 10 * [0xc101d000 - 0xc101dfff] mem
PCI: 00:0d.3 18 * [0xc101e000 - 0xc101efff] mem
PCI: 00:0f.0 10 * [0xc101f000 - 0xc101ffff] mem
PCI: 00:0f.1 10 * [0xc1020000 - 0xc1020fff] mem
PCI: 00:0f.2 10 * [0xc1021000 - 0xc1021fff] mem
PCI: 00:1f.1 10 * [0xc1022000 - 0xc10220ff] mem
DOMAIN: 0000 mem: next_base: c1022100 size: 11022100 align: 28 gran: 0 done
PCI: 00:13.0 prefmem: base:cfffffff size:0 align:20 gran:20 limit:cfffffff
PCI: 00:13.0 prefmem: next_base: cfffffff size: 0 align: 20 gran: 20 done
PCI: 00:13.0 mem: base:cfffffff size:0 align:20 gran:20 limit:cfffffff
PCI: 00:13.0 mem: next_base: cfffffff size: 0 align: 20 gran: 20 done
PCI: 00:13.1 prefmem: base:cfffffff size:0 align:20 gran:20 limit:cfffffff
PCI: 00:13.1 prefmem: next_base: cfffffff size: 0 align: 20 gran: 20 done
PCI: 00:13.1 mem: base:cfffffff size:0 align:20 gran:20 limit:cfffffff
PCI: 00:13.1 mem: next_base: cfffffff size: 0 align: 20 gran: 20 done
Root Device assign_resources, bus 0 link: 0
DOMAIN: 0000 assign_resources, bus 0 link: 0
PCI: 00:00.1 10 <- [0x00c1010000 - 0x00c1017fff] size 0x00008000 gran 0x0f mem64
PCI: 00:02.0 10 <- [0x00c0000000 - 0x00c0ffffff] size 0x01000000 gran 0x18 mem64
PCI: 00:02.0 18 <- [0x00b0000000 - 0x00bfffffff] size 0x10000000 gran 0x1c
prefmem64
PCI: 00:02.0 20 <- [0x0000001000 - 0x000000103f] size 0x00000040 gran 0x06 io
PCI: 00:0d.1 10 <- [0x00c1018000 - 0x00c1019fff] size 0x00002000 gran 0x0d mem64
PCI: 00:0d.1 18 <- [0x00c101c000 - 0x00c101cfff] size 0x00001000 gran 0x0c mem64
PCI: 00:0d.2 10 <- [0x00c101d000 - 0x00c101dfff] size 0x00001000 gran 0x0c mem
PCI: 00:0d.3 10 <- [0x00c101a000 - 0x00c101bfff] size 0x00002000 gran 0x0d mem64
PCI: 00:0d.3 18 <- [0x00c101e000 - 0x00c101efff] size 0x00001000 gran 0x0c mem64
PCI: 00:0f.0 10 <- [0x00c101f000 - 0x00c101ffff] size 0x00001000 gran 0x0c mem64
PCI: 00:0f.1 10 <- [0x00c1020000 - 0x00c1020fff] size 0x00001000 gran 0x0c mem64
PCI: 00:0f.2 10 <- [0x00c1021000 - 0x00c1021fff] size 0x00001000 gran 0x0c mem64
PCI: 00:13.0 1c <- [0x000000ef9f - 0x000000ef9e] size 0x00000000 gran 0x0c bus
01 io
PCI: 00:13.0 24 <- [0x00cfffffff - 0x00cffffffe] size 0x00000000 gran 0x14 bus
01 prefmem
PCI: 00:13.0 20 <- [0x00cfffffff - 0x00cffffffe] size 0x00000000 gran 0x14 bus
01 mem
PCI: 00:13.1 1c <- [0x000000ef9f - 0x000000ef9e] size 0x00000000 gran 0x0c bus
02 io
PCI: 00:13.1 24 <- [0x00cfffffff - 0x00cffffffe] size 0x00000000 gran 0x14 bus
02 prefmem
PCI: 00:13.1 20 <- [0x00cfffffff - 0x00cffffffe] size 0x00000000 gran 0x14 bus
02 mem
PCI: 00:15.0 10 <- [0x00c1000000 - 0x00c100ffff] size 0x00010000 gran 0x10 mem64
PCI: 00:1f.1 10 <- [0x00c1022000 - 0x00c10220ff] size 0x00000100 gran 0x08 mem64
DOMAIN: 0000 assign_resources, bus 0 link: 0
Root Device assign_resources, bus 0 link: 0
Done setting resources.
Show resources in subtree (Root Device)...After assigning values.
Root Device child on link 0 CPU_CLUSTER: 0
CPU_CLUSTER: 0 child on link 0 APIC: 00
APIC: 00
DOMAIN: 0000 child on link 0 PCI: 00:00.0
DOMAIN: 0000 resource base 1000 size 40 align 6 gran 0 limit ef9f flags
40040100 index 10000000
DOMAIN: 0000 resource base b0000000 size 11022100 align 28 gran 0 limit
cfffffff flags 40040200 index 10000100
PCI: 00:00.0
PCI: 00:00.0 resource base 0 size a0000 align 0 gran 0 limit 0 flags
e0004200 index 0
PCI: 00:00.0 resource base a0000 size 20000 align 0 gran 0 limit 0 flags
f0000200 index 1
PCI: 00:00.0 resource base c0000 size 40000 align 0 gran 0 limit 0 flags
f0004200 index 2
PCI: 00:00.0 resource base 7b000000 size 800000 align 0 gran 0 limit 0 flags
f0004200 index 3
PCI: 00:00.0 resource base 7b800000 size 4800000 align 0 gran 0 limit 0
flags f0004200 index 4
PCI: 00:00.0 resource base 7affe000 size 2000 align 0 gran 0 limit 0 flags
f0004200 index 5
PCI: 00:00.0 resource base 7abfe000 size 400000 align 0 gran 0 limit 0 flags
f0004200 index 6
PCI: 00:00.0 resource base 100000 size ff00000 align 0 gran 0 limit 0 flags
e0004200 index 7
PCI: 00:00.0 resource base 10000000 size 2151000 align 0 gran 0 limit 0
flags f0004200 index 8
PCI: 00:00.0 resource base 12151000 size 68aad000 align 0 gran 0 limit 0
flags e0004200 index 9
PCI: 00:00.0 resource base d0000000 size 10000000 align 0 gran 0 limit 0
flags f0000200 index a
PCI: 00:00.0 resource base fef00000 size 1000 align 0 gran 0 limit 0 flags
f0000200 index b
PCI: 00:00.0 resource base e0000000 size 10000000 align 0 gran 0 limit 0
flags f0000200 index c
PCI: 00:00.1
PCI: 00:00.1 resource base c1010000 size 8000 align 15 gran 15 limit
c1017fff flags 60000201 index 10
PCI: 00:02.0
PCI: 00:02.0 resource base c0000000 size 1000000 align 24 gran 24 limit
c0ffffff flags 60000201 index 10
PCI: 00:02.0 resource base b0000000 size 10000000 align 28 gran 28 limit
bfffffff flags 60001201 index 18
PCI: 00:02.0 resource base 1000 size 40 align 6 gran 6 limit 103f flags
60000100 index 20
PCI: 00:0d.0
PCI: 00:0d.1
PCI: 00:0d.1 resource base c1018000 size 2000 align 13 gran 13 limit
c1019fff flags 60000201 index 10
PCI: 00:0d.1 resource base c101c000 size 1000 align 12 gran 12 limit
c101cfff flags 60000201 index 18
PCI: 00:0d.2
PCI: 00:0d.2 resource base c101d000 size 1000 align 12 gran 12 limit
c101dfff flags 60000200 index 10
PCI: 00:0d.3
PCI: 00:0d.3 resource base c101a000 size 2000 align 13 gran 13 limit
c101bfff flags 60000201 index 10
PCI: 00:0d.3 resource base c101e000 size 1000 align 12 gran 12 limit
c101efff flags 60000201 index 18
PCI: 00:0f.0
PCI: 00:0f.0 resource base c101f000 size 1000 align 12 gran 12 limit
c101ffff flags 60000201 index 10
PCI: 00:0f.1
PCI: 00:0f.1 resource base c1020000 size 1000 align 12 gran 12 limit
c1020fff flags 60000201 index 10
PCI: 00:0f.2
PCI: 00:0f.2 resource base c1021000 size 1000 align 12 gran 12 limit
c1021fff flags 60000201 index 10
PCI: 00:11.0
PCI: 00:13.0
PCI: 00:13.0 resource base ef9f size 0 align 12 gran 12 limit ef9f flags
60080102 index 1c
PCI: 00:13.0 resource base cfffffff size 0 align 20 gran 20 limit cfffffff
flags 60081202 index 24
PCI: 00:13.0 resource base cfffffff size 0 align 20 gran 20 limit cfffffff
flags 60080202 index 20
PCI: 00:13.1
PCI: 00:13.1 resource base ef9f size 0 align 12 gran 12 limit ef9f flags
60080102 index 1c
PCI: 00:13.1 resource base cfffffff size 0 align 20 gran 20 limit cfffffff
flags 60081202 index 24
PCI: 00:13.1 resource base cfffffff size 0 align 20 gran 20 limit cfffffff
flags 60080202 index 20
PCI: 00:15.0
PCI: 00:15.0 resource base c1000000 size 10000 align 16 gran 16 limit
c100ffff flags 60000201 index 10
PCI: 00:1f.0
PCI: 00:1f.0 resource base d0000000 size 30000000 align 0 gran 0 limit 0
flags d0000200 index 10
PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0000100
index 0
PCI: 00:1f.1
PCI: 00:1f.1 resource base efa0 size 20 align 0 gran 0 limit efbf flags
f0000100 index 20
PCI: 00:1f.1 resource base c1022000 size 100 align 8 gran 8 limit c10220ff
flags 60000201 index 10
Done allocating resources.
Calling FspNotify(0x00000020)
ID:956 Time:#^!3049184225ID:957 Time:#^!3052380554BS: BS_DEV_RESOURCES times
(us): entry 0 run 4291791429 exit 7952
ID:50 Time:#^!3063924122Enabling resources...
PCI: 00:00.0 subsystem <- 0000/0000
PCI: 00:00.0 cmd <- 07
PCI: 00:00.1 cmd <- 02
PCI: 00:02.0 cmd <- 03
PCI: 00:0d.1 subsystem <- 0000/0000
PCI: 00:0d.1 cmd <- 106
PCI: 00:0d.2 subsystem <- 0000/0000
PCI: 00:0d.2 cmd <- 502
PCI: 00:0d.3 subsystem <- 0000/0000
PCI: 00:0d.3 cmd <- 106
PCI: 00:0f.0 cmd <- 06
PCI: 00:0f.1 cmd <- 06
PCI: 00:0f.2 cmd <- 06
PCI: 00:13.0 bridge ctrl <- 0003
PCI: 00:13.0 cmd <- 100
PCI: 00:13.1 bridge ctrl <- 0003
PCI: 00:13.1 cmd <- 100
PCI: 00:15.0 subsystem <- 0000/0000
PCI: 00:15.0 cmd <- 102
PCI: 00:1f.0 subsystem <- 0000/0000
PCI: 00:1f.0 cmd <- 107
PCI: 00:1f.1 subsystem <- 0000/0000
PCI: 00:1f.1 cmd <- 103
done.
BS: BS_DEV_ENABLE times (us): entry 0 run 70807 exit 0
ID:60 Time:#^!3162049979Initializing devices...
Root Device init ...
SMBUS transaction error
pmic version val = 0xffffffff
PMIC Version: PMIC_A0
SMBUS transaction error
SMBUS transaction error
SMBUS transaction error
Root Device init finished in 19331 usecs
CPU_CLUSTER: 0 init ...
CPU has 2 cores, 2 threads enabled.
Entering cbfs_boot_locate
Entering boot_device_init in boot_device.c
CBFS @ 0 size 1ffc40
CBFS: Locating 'cpu_microcode_blob.bin'
CBFS: 'cpu_microcode_blob.bin' not found.
CPU: Intel(R) Atom(TM) Processor E3930 @ 1.30GHz.
Loading module at 00030000 with entry 00030000. filesize: 0x140 memsize: 0x140
Processing 16 relocs. Offset value of 0x00030000
Attempting to start 1 APs
Waiting for 10ms after sending INIT.
Waiting for 1st SIPI to complete...AP: slot 1 apic_id 4.
done.
Waiting for 2nd SIPI to complete...done.
Open SMM.
Loading module at 00038000 with entry 00038000. filesize: 0x180 memsize: 0x180
Processing 10 relocs. Offset value of 0x00038000
SMM Module: stub loaded at 00038000. Will call 7a928eb7(00000000)
Installing SMM handler to 0x7b000000
Loading module at 7b010000 with entry 7b010046. filesize: 0x408 memsize: 0x4420
Processing 18 relocs. Offset value of 0x7b010000
Loading module at 7b008000 with entry 7b008000. filesize: 0x180 memsize: 0x180
Processing 10 relocs. Offset value of 0x7b008000
SMM Module: placing jmp sequence at 7b007c00 rel16 0x03fd
SMM Module: stub loaded at 7b008000. Will call 7b010046(00000000)
Initializing Southbridge SMI... ... pmbase = 0x0400
SMI# handler already enabled?
Boot UEFI payload, not set smrr here since it would disable SMRAM access
will set smrr in another place to ensure UEFI SMM code could work.
New SMBASE 0x7b000000
Relocation complete.
Boot UEFI payload, not set smrr here since it would disable SMRAM access
will set smrr in another place to ensure UEFI SMM code could work.
New SMBASE 0x7afffc00
Relocation complete.
Initializing CPU #0
CPU: vendor Intel device 506c9
CPU: family 06, model 5c, stepping 09
CPU #0 initialized
Initializing CPU #1
CPU: vendor Intel device 506c9
CPU: family 06, model 5c, stepping 09
CPU #1 initialized
Enabling SMIs.
Locking SMM.
Turbo is available and visible
cpu: frequency set to 1800
CPU_CLUSTER: 0 init finished in 205654 usecs
PCI: 00:00.0 init ...
PCI: 00:00.0 init finished in 2246 usecs
PCI: 00:00.1 init ...
PCI: 00:00.1 init finished in 2247 usecs
PCI: 00:02.0 init ...
PCI: 00:02.0 init finished in 2245 usecs
PCI: 00:0d.1 init ...
PCI: 00:0d.1 init finished in 2246 usecs
PCI: 00:0d.2 init ...
PCI: 00:0d.2 init finished in 2247 usecs
PCI: 00:0d.3 init ...
PCI: 00:0d.3 init finished in 2236 usecs
PCI: 00:0f.0 init ...
PCI: 00:0f.0 init finished in 2245 usecs
PCI: 00:0f.1 init ...
PCI: 00:0f.1 init finished in 2236 usecs
PCI: 00:0f.2 init ...
PCI: 00:0f.2 init finished in 2238 usecs
PCI: 00:13.0 init ...
Initializing PCH PCIe bridge.
PCI: 00:13.0 init finished in 5276 usecs
PCI: 00:13.1 init ...
Initializing PCH PCIe bridge.
PCI: 00:13.1 init finished in 5267 usecs
PCI: 00:15.0 init ...
PCI: 00:15.0 init finished in 2246 usecs
PCI: 00:1f.0 init ...
IOAPIC: Initializing IOAPIC at 0xfec00000
IOAPIC: Bootstrap Processor Local APIC = 0x00
IOAPIC: ID = 0x02
IOAPIC: Dumping registers
reg 0x0000: 0x02000000
reg 0x0001: 0x00770020
reg 0x0002: 0x00000000
PCI: 00:1f.0 init finished in 23257 usecs
PCI: 00:1f.1 init ...
PCI: 00:1f.1 init finished in 2257 usecs
Devices initialized
Show all devs... After init.
Root Device: enabled 1
CPU_CLUSTER: 0: enabled 1
APIC: 00: enabled 1
DOMAIN: 0000: enabled 1
PCI: 00:00.0: enabled 1
PCI: 00:0d.0: enabled 0
PCI: 00:0d.1: enabled 1
PCI: 00:0d.2: enabled 1
PCI: 00:0d.3: enabled 1
PCI: 00:11.0: enabled 0
PCI: 00:15.0: enabled 1
PCI: 00:13.0: enabled 1
PCI: 00:13.1: enabled 1
PCI: 00:18.1: enabled 1
PCI: 00:18.2: enabled 1
PCI: 00:1f.0: enabled 1
PCI: 00:1f.1: enabled 1
PCI: 00:00.1: enabled 1
PCI: 00:02.0: enabled 1
PCI: 00:0f.0: enabled 1
PCI: 00:0f.1: enabled 1
PCI: 00:0f.2: enabled 1
APIC: 04: enabled 1
BS: BS_DEV_INIT times (us): entry 0 run 414819 exit 1
Finalize devices...
Devices finalized
ID:70 Time:#^!3707667806BS: BS_POST_DEVICE times (us): entry 1 run 6252 exit 0
ID:75 Time:#^!3717715811BS: BS_OS_RESUME_CHECK times (us): entry 0 run 2346
exit 0
ID:80 Time:#^!3728261127smbios_write_tables: 7a8fb000
Create SMBIOS type 17
Root Device (Intel Leafhill)
CPU_CLUSTER: 0 (Intel Apollolake)
APIC: 00 (Intel Apollolake)
DOMAIN: 0000 (Intel Apollolake)
PCI: 00:00.0 (Intel Apollolake)
PCI: 00:0d.0 (Intel Apollolake)
PCI: 00:0d.1 (Intel Apollolake)
PCI: 00:0d.2 (Intel Apollolake)
PCI: 00:0d.3 (Intel Apollolake)
PCI: 00:11.0 (Intel Apollolake)
PCI: 00:15.0 (Intel Apollolake)
PCI: 00:13.0 (Intel Apollolake)
PCI: 00:13.1 (Intel Apollolake)
PCI: 00:18.1 (Intel Apollolake)
PCI: 00:18.2 (Intel Apollolake)
PCI: 00:1f.0 (Intel Apollolake)
PCI: 00:1f.1 (Intel Apollolake)
PCI: 00:00.1 (unknown)
PCI: 00:02.0 (unknown)
PCI: 00:0f.0 (unknown)
PCI: 00:0f.1 (unknown)
PCI: 00:0f.2 (unknown)
APIC: 04 (unknown)
SMBIOS tables: 415 bytes.
Writing table forward entry at 0x00000500
Wrote coreboot table at: 00000500, 0x10 bytes, checksum 554f
Table forward entry ends at 0x00000528.
... aligned to 0x00001000
Writing coreboot table at 0x7a8f3000
rom_table_end = 0x7a8f3000
... aligned to 0x7a900000
0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
1. 0000000000001000-000000000009ffff: RAM
2. 00000000000a0000-00000000000fffff: RESERVED
3. 0000000000100000-000000000fffffff: RAM
4. 0000000010000000-0000000012150fff: RESERVED
5. 0000000012151000-000000007a8f2fff: RAM
6. 000000007a8f3000-000000007affffff: CONFIGURATION TABLES
7. 000000007b000000-000000007fffffff: RESERVED
8. 00000000d0000000-00000000ffffffff: RESERVED
try to get the flash device in lb_spi_flash
Entering boot_device_init in boot_device.c
Entering lb_boot_media_params
Entering boot_device_init in boot_device.c
CBFS @ 0 size 1ffc40
Entering find_fmap_directory
Entering boot_device_init in boot_device.c
Wrote coreboot table at: 7a8f3000, 0x1d4 bytes, checksum 9864
coreboot table: 492 bytes.
IMD ROOT 0. 7afff000 00001000
IMD SMALL 1. 7affe000 00001000
FSP MEMORY 2. 7abfe000 00400000
TIME STAMP 3. 7abfd000 000002e0
ROMSTG STCK 4. 7abf8000 00005000
ROMSTG RAM 5. 7abf0000 0000746c
OBB IMAGE 6. 7a9f0000 00200000
RAMSTAGE 7. 7a926000 000ca000
REFCODE 8. 7a8fc000 0002a000
SMBIOS 9. 7a8fb000 00000800
COREBOOT 10. 7a8f3000 00008000
IMD small region:
IMD ROOT 0. 7affec00 00000400
CAR GLOBALS 1. 7affea80 00000180
POWER STATE 2. 7affea40 00000040
FSP RUNTIME 3. 7affea20 00000008
MEM INFO 4. 7affe8c0 00000141
ROMSTAGE 5. 7affe8a0 00000004
GDT 6. 7affe6a0 00000200
ACPI GNVS 7. 7affe520 00000163
BS: BS_WRITE_TABLES times (us): entry 0 run 249057 exit 0
ID:90 Time:#^!4056088591Entering asset_locate
Entering boot_device_init in boot_device.c
CBFS provider active.
Entering cbfs_boot_locate
Entering boot_device_init in boot_device.c
CBFS @ 0 size 1ffc40
CBFS: Locating 'fallback/payload'
CBFS: Found @ offset 3f600 size 4ac
'fallback/payload' located at offset: 3f638 size: 4ac
Loading segment from rom address 0x7aa2f638
code (compression=1)
New segment dstaddr 0x100000 memsize 0x8b4 srcaddr 0x7aa2f6a8 filesize 0x418
Loading segment from rom address 0x7aa2f654
BSS 0x00102000 (16 byte)
Loading segment from rom address 0x7aa2f670
data (compression=0)
New segment dstaddr 0x80480f4 memsize 0x24 srcaddr 0x7aa2fac0 filesize 0x24
Loading segment from rom address 0x7aa2f68c
Entry Point 0x0010001e
Loading Segment: addr: 0x0000000000100000 memsz: 0x00000000000008b4 filesz:
0x0000000000000418
lb: [0x000000007a927000, 0x000000007a9efc40)
Post relocation: addr: 0x0000000000100000 memsz: 0x00000000000008b4 filesz:
0x0000000000000418
using LZMA
ID:15 Time:#^!4184703705ID:16 Time:#^!4188047448[ 0x00100000, 001008b4,
0x001008b4) <- 7aa2f6a8
dest 00100000, end 001008b4, bouncebuffer ffffffff
Loading Segment: addr: 0x0000000000102000 memsz: 0x0000000000000010 filesz:
0x0000000000000000
lb: [0x000000007a927000, 0x000000007a9efc40)
Post relocation: addr: 0x0000000000102000 memsz: 0x0000000000000010 filesz:
0x0000000000000000
Loading Segment: addr: 0x00000000080480f4 memsz: 0x0000000000000024 filesz:
0x0000000000000024
lb: [0x000000007a927000, 0x000000007a9efc40)
Post relocation: addr: 0x00000000080480f4 memsz: 0x0000000000000024 filesz:
0x0000000000000024
it's not compressed!
[ 0x080480f4, 08048118, 0x08048118) <- 7aa2fac0
dest 080480f4, end 08048118, bouncebuffer ffffffff
Loaded segments
Coreboot FSP Performance Data
ID: 950 - 951: 2651627365 - 2426975730 --> 172ms
ID: 952 - 953: #^!234044777 - 2741745790 --> 1374ms
ID: 954 - 955: #^!761110170 - #^!540304572 --> 169ms
ID: 956 - 957: #^!3052380554 - #^!3049184225 --> 2ms
Calling FspNotify(0x00000040)
ID:958 Time:#^!20291489ID:959 Time:#^!24672040Finalizing chipset.
BS: BS_PAYLOAD_LOAD times (us): entry 0 run 174820 exit 34330
Calling FspNotify(0x000000f0)
ID:956 Time:#^!41994679ID:957 Time:#^!50577561Jumping to boot code at
0010001e(7a8f3000)
ID:99 Time:#^!59018449CPU0: stack: 7a961000 - 7a962000, lowest used address
7a96190c, stack used: 1780 bytes
coreboot-APOLLOLAKE_CB_MR4_001 Wed Nov 7 09:44:01 UTC 2018 verstage starting...
FSP TempRamInit successful
0xfef15ff0: fsp_boot_context
0x000000003363ef31: tsc
0xffffdc94: fih
0x00000000: bist
0x5aa55aa5: hash
FSP_INFO_HEADER: ffffdc94
FSP Signature: $APLFSP$
FSP Header Version: 3
FSP Revision: 1.4.3.1
Entering cbfs_boot_locate
Entering boot_device_init in boot_device.c
CBFS @ 0 size 7c40
CBFS: Locating 'verstage.rel'
CBFS: Found @ offset 1f00 size 14c
verstage is relocated from ffff8054 to 0xfef07054
CPU: frequency set to 1300 MHz
Entering asset_locate
Entering boot_device_init in boot_device.c
CBFS provider active.
Entering cbfs_boot_locate
Entering boot_device_init in boot_device.c
CBFS @ 0 size 70000
CBFS: Locating 'fallback/romstage'
CBFS: Found @ offset 0 size 6488
'fallback/romstage' located at offset: 38 size: 6488
CSE IBB verification result: 1
ID:18 Time:1764658Entering cbfs_boot_locate
Entering boot_device_init in boot_device.c
CBFS @ 0 size 70000
CBFS: Locating 'fsp.bin'
CBFS: Found @ offset 16ec0 size 59000
ID:1 Time:2292335265
coreboot-APOLLOLAKE_CB_MR4_001 Wed Nov 7 09:44:01 UTC 2018 romstage starting...
bist: 0x00000000
tsc_low: 0x00000000
tsc_hi: 0x00000000
CONFIG_MMCONF_BASE_ADDRESS: 0xe0000000
Using: FSP 2.0
FSP_INFO_HEADER: fef56f94
FSP Signature: $APLFSP$
FSP Header Version: 3
FSP Revision: 1.4.3.1
PM1_STS: 0000
PM1_EN: 0000
PM1_CNT: 00000000
TCO_STS: 0000 0000
GPE0_STS: 00000000 00000000 00000000 00000000
GPE0_EN: 00000000 00000000 00000000 00000000
Previous Sleep State: S0
CPU: Intel(R) Atom(TM) Processor E3930 @ 1.30GHz
CPU: ID 506c9, Apollolake B0, ucode: 00000026
CPU: AES supported, TXT NOT supported, VT supported
CPU: frequency set to 1300 MHz
ID:2 Time:2380755396WEAK: src/soc/intel/common/romstage.c/mrc_cache_get_current
called
No MRC cache found.
WEAK: src/soc/intel/common/romstage.c/mainboard_check_ec_image called
UPD Data: 0xfef57024
PreMemGpioTablePtr: 0x0
Calling FspMemoryInit: 0xfef572f8
0x00000000: NvsBufferPtr
0xfef1546c: FspmConfig
0xfef153f0: HobListPtr
ID:950 Time:2424435005ID:951 Time:2624954982FspMemoryInit returned 0x00000000
Reserving 0x0000000000400000 bytes from 0x000000007abfe000 for FSP
0x00800000: smm_size
0x7b000000: smm_base
0x7b000000: cbmem_top
CBMEM:
IMD: root @ 7afff000 254 entries.
IMD: root @ 7affec00 62 entries.
smm_subregion:1, start=0x7b700000, size=0x100000
External stage cache:
IMD: root @ 7b7ff000 254 entries.
IMD: root @ 7b7fec00 62 entries.
0x7abfe000: fsp_reserved_memory_area
ID:3 Time:2681446726MRC data at 7ac1f0d0 45792 bytes
WEAK: src/soc/intel/common/romstage.c/mrc_cache_stash_data called
CBMEM entry for DIMM info: 0x7affe8c0
1 DIMMs found
WEAK: src/soc/intel/common/romstage.c/soc_after_ram_init called
Calling FspTempRamExit API
ID:952 Time:2715136024Entering cbfs_boot_locate
Entering boot_device_init in boot_device.c
CBFS @ 0 size 70000
CBFS: Locating 'romstage.rel'
CBFS: Found @ offset 64c0 size 480
romstage is relocated from fef40054 to 0x7abf1000--
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