Correct memory settings were found in datasheet. FSP has been configured from
configurator. However, incorrect settings of memory in the device tree were
priority and therefore the memory was initialized incorrectly. By changing the
device tree, the problem was fixed.
From: Alex Feinman
Sent: Wednesday, November 07, 2018 1:20 AM
To: Alexey Borovikov ; R S
Cc: [email protected]
Subject: Re: [coreboot] How to get correct memory params for FSP
This tells us nothing about swizzling - the order in which DQ/DQS lines of the
memory address bus are connected to the CPU. Memory connections to the CPU are
flexible to simplify PCB routing. As a result in order for the memory
controller to be able to use memory you need to provide board-specific mapping.
You cannot glean this from looking at the PCB - you need the schematic. And no,
off the shelf Tianocore will not automatically do this either - it's a
customizable part of the build
--------------------------------------------------------------------------------
From: Alexey Borovikov <[email protected]>
Sent: Tuesday, November 6, 2018 11:06 AM
To: R S; [email protected]
Cc: [email protected]
Subject: Re: [coreboot] How to get correct memory params for FSP
Ok, there is no spd on the board. Four memory chips are soldered on the board
(Micron DDR3L 4х512MB 1333Mhz). I understand that I need to set the correct
memory parameters in the fsp configurator. Even if it works, replacing the
memory chips may lead to a stop working of the coreboot.rom. It is necessary to
change the parameters of the fsp again and rebuild coreboot.rom.
How does the proprietary BIOS (TianoCore) work in case of replacing the memory
chips on board?
Are there universal parameters for this memory types and what should I take
note for when configuring FSP?
From: R S
Sent: Tuesday, November 06, 2018 8:30 PM
To: [email protected]
Cc: [email protected] ; [email protected]
Subject: Re: [coreboot] How to get correct memory params for FSP
Faint memories... are you the ISO recorder author from 15 years ago?
On Tue, Nov 6, 2018 at 12:23 PM Alex Feinman <[email protected]> wrote:
The two major issues with bringing up the memory subsystem on a new board are
SPD parameters and DQ/DQS layout
Specifically, if you look at the apollolake rvp subtree, you can see a whole
bunch of parameters being set in romstage.c. Some of it is fairly
straightforward. Swizzling tables are not and require you to be able to read
schematic (and have access to it in the first place)
Obviously, the problem could be elsewhere. I would start with enabling MRC
debug and perhaps posting the MRC output
------------------------------------------------------------------------------
From: coreboot <[email protected]> on behalf of Alexey Borovikov
via coreboot <[email protected]>
Sent: Saturday, November 3, 2018 5:38 AM
To: [email protected]
Subject: [coreboot] How to get correct memory params for FSP
Hi.
I port the Coreboot to a board with an SOC Intel Atom E3845 and use FSP for
the Baytrail family. The result - postcode is 0x2A. From the descriptions on
the Internet, I understand that the problem is in the incorrect memory
parameters.
Question: are there any utilities or methods that will help to get the
correct memory parameters when working a regular BIOS from Linux or Windows
systems?
Many thanks!
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