set PcdSmbusSpdWriteDisable to disable? On Mon, Jan 14, 2019 at 8:28 PM Hilbert Tu(杜睿哲_Pegatron) < hilbert...@pegatroncorp.com> wrote:
> Hi, > > Is there anyone can tell me how to change MCTRL.SPDDIS in Coreboot? > > > > The Intel Denverton blocks write permission to address A0~AE due to > security concern of DIMM SPD, but this also restricts the write access to > generic EEPROM access in our platform. So I need to modify the SPDDIS bit > to bypass the protection. But I don’t know how to do that in Coreboot. > Please help and thanks in advance. > > > > -Hilbert > This e-mail and its attachment may contain information that is > confidential or privileged, and are solely for the use of the individual to > whom this e-mail is addressed. If you are not the intended recipient or > have received it accidentally, please immediately notify the sender by > reply e-mail and destroy all copies of this email and its attachment. > Please be advised that any unauthorized use, disclosure, distribution or > copying of this email or its attachment is strictly prohibited. > 本電子郵件及其附件可能含有機密或依法受特殊管制之資訊，僅供本電子郵件之受文者使用。台端如非本電子郵件之受文者或誤收本電子郵件，請立即回覆郵件通知寄件人，並銷毀本電子郵件之所有複本及附件。任何未經授權而使用、揭露、散佈或複製本電子郵件或其附件之行為，皆嚴格禁止。 > > _______________________________________________ > coreboot mailing list -- coreboot@coreboot.org > To unsubscribe send an email to coreboot-le...@coreboot.org >
_______________________________________________ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-le...@coreboot.org
