Hi Patrick, I noticed in your patch you are calling this host CPU based clearing after the return from FSP memory initialization. If you are calling this in a system with ECC memory, this step is redundant. Part of the initialization of ECC enabled memory is to write a pattern to all of memory to setup the ECC code. Additionally the memory initialization is using a HW engine to achieve a bandwidth that is not possible by a SW host CPU based mechanism. This is an interesting idea and could be useful, however in this specific case you would be adding boot overhead unnecessarily.
Steve Mooney Senior Consulting Engineer SysPro Consulting, LLC https://www.sysproconsulting.com/ -----Original Message----- From: Patrick Rudolph <[email protected]> Sent: Tuesday, February 26, 2019 7:36 AM To: Coreboot <[email protected]> Subject: [coreboot] New API to clear DRAM at boot Hi coreboot folks, in order to support TEE like Intel TXT it is necessary to be able to clear all DRAM at boot on request. As all of the x86 coreboot code is x86_32, it is necessary to make use of PAE to clear memory. Please find the attached patch series which proposes an architecure independed API, PAE enabled memset on x86, and helper functions to clear all DRAM on Broadwell DE: https://review.coreboot.org/#/q/project:coreboot+branch:master+topic:security_dram_clear The code can be easily extended to other platforms. Please comment, test and improve the patchset. Regards, -- Patrick Rudolph 9elements Agency GmbH, Kortumstraße 19-21, 44787 Bochum, Germany Email: [email protected] Phone: +49 234 68 94 188 Sitz der Gesellschaft: Bochum Handelsregister: Amtsgericht Bochum, HRB 17519 Geschäftsführung: Sebastian Deutsch, Daniel Hoelzgen _______________________________________________ coreboot mailing list -- [email protected] To unsubscribe send an email to [email protected] _______________________________________________ coreboot mailing list -- [email protected] To unsubscribe send an email to [email protected]
