On Fri, May 24, 2019 at 5:23 PM Дмитрий Понаморев <[email protected]> wrote: > > Thank for help! > > The LPC_CLKOUT1 clock signal appeared but there is no nuvoton chip detected > in linux. >
Well couple things you need to check in the hardware then: Probe the LPC FRAME signal or use a logic analyzer to see if there is any LPC activity while you run util/superiotool. Check from Nuvoton datasheet if it requires LPC CLK to be present before its RESET signal is de-asserted. Check if Nuvoton has otherwise a sane power-up sequence (Vcc, Vstb rise-up vs RESET pins). > I could not turn off the SOC UART yet. With my changes, the system does not > start well (stops at post code 0x46, 0x47). Disable coreboot console output to serial port for now. When neither UART is present, it might just be hitting transmit timeout for every single character, making it boot ridiculously slow. If you can boot to OS, you can still read the logs with util/cbmem. > And the most important thing is that the Nuvoton System Clock (48 MHz for the > baud generator of the UARTs) is missing. This may be preventing util/superiotool from detecting the chip. I think I have seen some SIO parts respond to ID queries even without this clock if LPC CLK is present. > How can I change the IDT clock synthesizer (9VRS4420DKLFT) settings in > coreboot? Rather, where can I make changes in coreboot to properly configure > IDT clock synthesizer (9VRS4420DKLFT)? Grep the source for smbus_block_write. There is drivers/ck505 and lenovo/x201 that you can use as base for your modifications. Sometimes these IDT datasheets are hard to get and you may need to capture the correct commands from SMBus signals or with utilities from i2c-tools package after booting with OEM firmware. Kyösti _______________________________________________ coreboot mailing list -- [email protected] To unsubscribe send an email to [email protected]
