Dne 30. 07. 19 v 11:18 Kinky Nekoboi napsal(a): > loading the microcode via Linux Kernel works. > > including it via coreboot causes General Protection Faults.
It fails on MSR write: 17.170377] RSP: 0018:ffffffff9d003e10 EFLAGS: 00010046 [ 17.175699] RAX: 0000000000000001 RBX: ffff8b289d93a040 RCX: 0000000000000049 The RCX is set to 0x49 which is the new IBPB barrier MSR. [ 17.151362] Code: 7d 08 49 83 c5 18 4c 89 fa 31 f6 e8 1e 68 99 00 49 8b 45 00 48 85 c0 75 e5 e9 73 ff ff ff b9 49 00 00 00 b8 01 00 00 00 31 d2 <0f> 30 e9 86 fc ff ff e9 81 00 00 00 48 c7 c2 e0 18 02 00 31 c0 65 And failing opcode is WRMSR (0f 30) Failing CPU is CPU 0, which is not what I was hoping for. My hypothesis was that maybe some of the processors are not receiving the microcode update properly. I would expect that CPU0 would have it correctly. For some reason CPU is advertising that it can do IBPB via CPUID but still failing to do that in reality. Very strange. Thanks, Rudolf _______________________________________________ coreboot mailing list -- [email protected] To unsubscribe send an email to [email protected]
