On Thu, Sep 19, 2019 at 3:20 AM Matt B <[email protected]> wrote: > > > Kyösti Mälkki said: >> >> AFAICS, that platform codebase even suffers from cache coherency issues >> while executing from cache-as-ram; there has been indications that increased >> spinlock usage in romstage causes boot failures and/or reset loops. > > > Where do you see this? Has it been reported?
It was the plausible reason for the revert: https://review.coreboot.org/c/coreboot/+/30830 where seemingly legit code change trigger bugs. Like with many RAM related problems on same platform(s) running with upstream coreboot, those with hardware have not bisected or debugged this further to have definite answers. I can tell AGESA fam14 has issues with AP's accessing CAR. >> Implementation of HyperTransport requires maintaining some pretty strange >> (or poor-quality) code for both static devicetree and PCI subsystem. > > > Which code? How can it be improved? Unless platform meets release requirements, there will be a commit to remove offending/bad code with explanations. As noted earlier, pretty much none of the promises from last five years to debug/bisect/improve, by various people on the mailing list, have not been fulfilled. My goodwill with fam10-15 is long gone. Regards, Kyösti Mälkki _______________________________________________ coreboot mailing list -- [email protected] To unsubscribe send an email to [email protected]
