On 14.11.2019 08:48, Jorge Fernandez Monteagudo wrote:
> Hi Michal!
>
>> Under config VBOOT. And define the CMOS offset for vboot in Kconfig as
>> in the patch linked earlier. AGESA binary typically have to reside under
>> certain offset in the binary, so you have to pass the AGESA name to be
>> added to RO partition only in menuconfig of vboot, since it should
>> probably reside there.
> Maybe do you refer to the AMD firmware instead of AGESA? I've seen in
> src/soc/amd/stoneyridge/Makefile.inc when the AMDFW_OUTSIDE_CBFS
> the amdfw.rom is the firmware to copy in a fixed position inside ROM. In
> src/soc/amd/stoneyridge/Kconfig you can see that they define RO_REGION_ONLY
> with the default 'apu/amdfw'
No, AMDFW which comprises PSP firmware and other components lies at
offset 0x20000 from the beginning of the flash (typically). AGESA is a
silicon initialization code which lies on different offsets (usually
0xFFE00000) and has to be in the RO region, because this is the range of
addresses it fits to (its nearly the bottom of the flash). Putting AGESA
in RW_A is impossible, because RW_A is not in the range of addresses
where AGESA should be placed, thus the previous error.
>
> Anyway, I've tried changing the flash size to 16MB to see the component's
> distribution. I've modified your file a little:
>
> FLASH@0xff800000 0x1000000 {
> RW_UNUSED@0x0 0x20000
> AMDFW(PRESERVE)@0x20000 0x90000
> SI_BIOS@0xb0000 0xF50000 {
> RW_SECTION_A 0x500000 {
> VBLOCK_A 0x10000
> FW_MAIN_A(CBFS)
> RW_FWID_A 0x40
> }
> CONSOLE 0x10000
> SMMSTORE(PRESERVE) 0x40000
> RW_VPD(PRESERVE) 0x4000
> WP_RO {
> FMAP@0x0 0x800
> RO_FRID 0x40
> RO_FRID_PAD 0x7c0
> RO_VPD(PRESERVE) 0x4000
> GBB 0x1e000
> COREBOOT(CBFS)
> }
> }
> }
If You do not have 16MB flash you won't be able to flash it with
flashrom. Secondly the base address of 0xff80000 should change in such
situation.
>
> Now, the CBFS is created ok:
>
> Created CBFS (capacity = 10325976 bytes)
> Created CBFS (capacity = 5177240 bytes)
> CBFS AGESA
> CBFS fallback/romstage
> CBFS fallback/ramstage
> CBFS cmos_layout.bin
> CBFS pci1002,9874.rom
> CBFS fallback/dsdt.aml
> CBFS fallback/payload
> CBFS AGESA
> CBFS fallback/ramstage
> CBFS pci1002,9874.rom
> CBFS fallback/dsdt.aml
> CBFS fallback/payload
> DD Adding AMD Firmware
> CBFS coreboot.rom
> CBFSLAYOUT coreboot.rom
>
> This image contains the following sections that can be manipulated with this
> tool:
>
> 'RW_UNUSED' (size 131072, offset 0)
> 'AMDFW' (preserve, size 589824, offset 131072)
> 'VBLOCK_A' (size 65536, offset 720896)
> 'FW_MAIN_A' (CBFS, size 5177280, offset 786432)
> 'RW_FWID_A' (size 64, offset 5963712)
> 'CONSOLE' (size 65536, offset 5963776)
> 'SMMSTORE' (preserve, size 262144, offset 6029312)
> 'RW_VPD' (preserve, size 16384, offset 6291456)
> 'RO_FRID' (size 64, offset 6309888)
> 'RO_FRID_PAD' (size 1984, offset 6309952)
> 'RO_VPD' (preserve, size 16384, offset 6311936)
> 'GBB' (size 122880, offset 6328320)
> 'COREBOOT' (CBFS, size 10326016, offset 6451200)
It doesn't mean it will work...
> It is possible to perform either the write action or the CBFS add/remove
> actions on every section listed above.
> To see the image's read-only sections as well, rerun with the -w option.
> CBFSPRINT coreboot.rom
>
> FMAP REGION: COREBOOT
> Name Offset Type Size Comp
> cbfs master header 0x0 cbfs header 32 none
> fallback/romstage 0x80 stage 65316 none
> fallback/ramstage 0x10040 stage 68406 none
> cmos_layout.bin 0x20bc0 cmos_layout 1548 none
> pci1002,9874.rom 0x21240 optionrom 64512 none
> fallback/dsdt.aml 0x30ec0 raw 6656 none
> fallback/payload 0x32940 simple elf 2627360 none
> (empty) 0x2b40c0 null 5394136 none
> AGESA 0x7d8fc0 raw 690436 none
> (empty) 0x881940 null 1405592 none
> bootblock 0x9d8c00 bootblock 944 none
> FMAP REGION: FW_MAIN_A
> Name Offset Type Size Comp
> fallback/ramstage 0x0 stage 68406 none
> pci1002,9874.rom 0x10b80 optionrom 64512 none
> fallback/dsdt.aml 0x20800 raw 6656 none
> fallback/payload 0x22280 simple elf 2627360 none
> (empty) 0x2a3a00 null 312664 none
> AGESA 0x2eff80 raw 690436 none
> (empty) 0x398900 null 1406616 none
>
Yes, you can add or remove components freely with cbfstool.
> Here you can see the line with the copy of the firmware:
>
> DD Adding AMD Firmware
>
> The code is in 'southbridge/amd/pi/hudson/Makefile.inc' and they do:
>
> dd if=$(obj)/amdfw.rom \
> of=$(obj)/coreboot.pre conv=notrunc bs=1 seek=131072 >/dev/null
> 2>&1
>
> to copy 'amdfw.rom' to the AMDFW(PRESERVE) in the flashmap.
>
>
> I think in a 8MB flash there is no room to the CBFS and a copy in the
> RW_SECTION_A.
> Is it possible to enable VBOOT and don't have a RW_SECTION_A? I'm not
> interested in
> recover the firmware...
Not exactly. This code puts AMDFW always at offset of 0x20000 from the
beginning of flash. It has nothing to do with CBFS if AMDFW_OUTSIDE_CBFS
is selected.
You need at least 1 RW slot, otherwise:
https://review.coreboot.org/c/coreboot/+/34977
you will end in a boot loop.
Regards,
Michał
>
> Thanks
> Jorge
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--
Michał Żygowski
Firmware Engineer
http://3mdeb.com | @3mdeb_com
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