Dear coreboot folks,
Despite ever increasing flash ROM chip sizes, small images are still
desired for faster boot times, faster flash times, and more space for
payloads, which is sometimes needed for adding several payloads
(including GRUB/TianoCore) or Linux payloads.
Jacob Garber did great work to achieve this goal by enabling Link Time
Optimization (LTO) for coreboot [1] and libpayload [2]. While doing
this, he also found and fixed several bugs in the code base.
Currently, it fails for AMD AGESA boards due handling of illegal globals.
Yes, this is a current limitation of LTO right now. Because the
object files are all lumped together into a single unit, all
information about where the symbols came from is lost, so
EXCLUDE_FILE is unable of excluding the AGESA objects from the
illegal_globals check. Tracing where a symbol came from has been
implemented in LLVM [0], but I'm not sure if it's on the roadmap for
GCC. For now it's probably best to disable LTO when compiling AGESA.
[0]: https://llvm.org/devmtg/2017-10/slides/LTOLinkerScriptsEdlerVonKoch.pdf
If somebody has a solution for that, that’d be great.
It’d be great, if more people could test this, on your boards, and
report back.
I propose, to submit the change-sets before the next release, and to
enable LTO for libpayload by default, and to disable it for coreboot by
default.
Big thanks again to Jacob for doing this. (My attempt doing this for
GRUB failed. ;-))
Kind regards,
Paul
[1]: https://review.coreboot.org/c/coreboot/+/38989
[2]: https://review.coreboot.org/c/coreboot/+/38291
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