On Tue, Apr 28, 2020 at 04:16:59PM +0200, Paul Menzel wrote: > Dear coreboot folks, > > > Despite ever increasing flash ROM chip sizes, small images are still desired > for faster boot times, faster flash times, and more space for > payloads, which is sometimes needed for adding several payloads > (including GRUB/TianoCore) or Linux payloads. > > Jacob Garber did great work to achieve this goal by enabling Link Time > Optimization (LTO) for coreboot [1] and libpayload [2]. While doing > this, he also found and fixed several bugs in the code base. > > Currently, it fails for AMD AGESA boards due handling of illegal globals. > > If somebody has a solution for that, that’d be great. > > It’d be great, if more people could test this, on your boards, and report > back. > > I propose, to submit the change-sets before the next release, and to enable > LTO for libpayload by default, and to disable it for coreboot by default. > > Big thanks again to Jacob for doing this. (My attempt doing this for GRUB > failed. ;-)) > > > Kind regards, > > Paul > > > [1]: https://review.coreboot.org/c/coreboot/+/38989 > [2]: https://review.coreboot.org/c/coreboot/+/38291
Hey Paul, thanks for the encouraging words. :) I tidied up the patches today and think they are ready for review. Not all targets compile yet, but all of the LTO framework is there so people can test it out with their boards. For example, the Thinkpad T500 boots successfully, and there is about a 10% reduction in stage size and compilation time. Right now I think it's safest to leave LTO disabled for libpayload and coreboot. GCC 9 is the first version where LTO is considered "production ready", and until we have that merged I think LTO should be considered experimental. Once people have had some time to try it out and work out any bugs we can move to making it the default in some cases. Cheers, Jacob _______________________________________________ coreboot mailing list -- [email protected] To unsubscribe send an email to [email protected]
