All, Some of you have seen in my mainboard port [1] that I'm trying to make a couple dozen configuration changes to my board's Super I/O chip the NCT6779D.
My initial attempt to describe them in devicetree.cb was ignored because they were not fully described in superio/nuvoton/nct6779d/superio.c as resources. Configuring them in bootblock (or romstage) raises another dilemma: Either I iterate over an array of register/value pairs at the expense of code readability, or code them directly with pnp_write_config() at the expense of bigger code size. And in either case it seems not all changes I made stick in the end (i.e. when looked at using superiotool -d). Then I investigated if I can modify ramstage. The pnp_info struct in superio.c has a 32-bit flag to describe available configuration registers. Each register in 0xf0~0xfe are individually covered by one bit in the flag, taking 15 bits. Much of my config needs lie in the 0xe0~0xee range, meaning another 15 bits and no room in this value to cover them all. Grouping multiple registers into one bit (eg. one bit represents 0xe0~0xe3 as registers we can set in devicetree.cb) isn't practical either because no two Super I/Os will have the same register layout. So this method is insufficient and I cannot extend it. Another approach is to introduce eg. a "reg" keyword that would let me set a value into register whatever, thereby shifting responsibility for correctness to the contributor. Unfortunately I know nothing about how sconfig works or how devicetree.cb get parsed into C code that get called in ramstage, so I could not just do it myself. Bottom line is, I need a way to make many configuration changes to multiple logical devices that are in registers 0xe0-0xfe. Ideas? Or there's one I overlooked? Thanks Keith [1] https://review.coreboot.org/c/coreboot/+/38988 _______________________________________________ coreboot mailing list -- [email protected] To unsubscribe send an email to [email protected]
