If I recall correctly, SPI flash is not memory mapped initially, apl just loads ibb i.e., bootblock in PCH memory & CPU executes from there. I guess bios flash mapping/decoding has to be enabled to allow CPU to access memory mapped SPI flash.
On Tue, Dec 1, 2020 at 5:14 PM Anatolii Vorobev <[email protected]> wrote: > Hi, Maxim. Sure, I’ve attached .config file. > > Here is cbfstool output: > > > > ./build/cbfstool build/coreboot.rom print > > FMAP REGION: COREBOOT > > Name Offset Type Size Comp > > cbfs master header 0x0 cbfs header 32 none > > fallback/romstage 0x80 stage 48164 none > > cpu_microcode_blob.bin 0xbd00 microcode 48128 none > > fallback/ramstage 0x17980 stage 106068 none > > vgaroms/seavgabios.bin 0x31840 raw 28160 none > > config 0x386c0 raw 283 none > > revision 0x38840 raw 681 none > > fallback/dsdt.aml 0x38b40 raw 6338 none > > fspm.bin 0x3a480 fsp 364544 none > > vbt.bin 0x934c0 raw 1299 LZMA (6154 > decompressed) > > payload_revision 0x93a40 raw 235 none > > (empty) 0x93b80 null 1048 none > > fsps.bin 0x93fc0 fsp 176128 none > > fallback/postcar 0xbf000 stage 22064 none > > fallback/payload 0xc4680 simple elf 69275 none > > payload_config 0xd5580 raw 1760 none > > (empty) 0xd5cc0 null 11137752 none > > bootblock 0xb74fc0 bootblock 32768 none > > > > Best Regards, > > Anatolii Vorobev > > > > *From:* Maxim Polyakov <[email protected]> > *Sent:* Tuesday, December 1, 2020 2:05 PM > *To:* Anatolii Vorobev <[email protected]> > *Cc:* [email protected] > *Subject:* Re: [coreboot] Apollo Lake cannot load coreboot > > > > Hi! > > Could you please send your .config ? > > The following command will help you find out which sections have been > added to the image: > > (coreboot dir)$ ./build/cbfstool build/coreboot.rom print > > Please send the output > > // Regards, > > // Max > > > > > > вт, 1 дек. 2020 г. в 13:13, Anatolii Vorobev <[email protected] > >: > > Dear community, > > I’m trying to bring up custom motherboard with Apollo Lake e3950 SoC. The > first thing I’ve tried is flashed UP Squared-based BIOS compiled using this > instructions: https://doc.coreboot.org/mainboard/up/squared/index.html > > After I run the motherboard it showed this uart0 output: > > > > coreboot-4.12-4087-g6aaf7db719-dirty Tue Nov 17 09:50:24 UTC 2020 > bootblock starting (log level: 7)... > > No FMAP found at 300000 offset. > > No FMAP found at 300000 offset. > > POST: 0xe0 > > Couldn't load romstage. > > > > After some time spent trying to figure out the reason of such problem I > found out that bootblock cannot load FMAP into RAM. I printed out some > parts of ram where romstage and FMAP should be and there where only 0xff > values. Looks like bootblock can’t map SPI flash data to RAM although flash > image has romstage and FMAP regions. The strange thing is that bootblock is > loaded ok but any further load (FMAP) fails. Any ideas what can be the > cause of this and how can I debug this thing? > > > > PS I tried flashing another BIOS (from AMI) and it passes CAR stage, FSP > stage, it even successfully initializes/trains DDR and so on. But coreboot > BIOS somehow fails on the very early stages. > > > > Best Regards, > > Anatolii Vorobev > > _______________________________________________ > coreboot mailing list -- [email protected] > To unsubscribe send an email to [email protected] > > _______________________________________________ > coreboot mailing list -- [email protected] > To unsubscribe send an email to [email protected] >
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