Hi Sheng, On Wed, Oct 27, 2021 at 1:19 AM Tan, Lean Sheng <[email protected]> wrote:
> Hi all, > This is an info mail for addressing this patch (soc/intel/elkhartlake: > Introduce Intel PSE [1]): > With the Elkhart Lake Platform Intel has introduced an additional > subsystem controller inside the Chipset which can be used to offload > different kind of tasks from the main CPU. > This controller is called the Programmable Service Engine (PSE) and is an > ARM Cortex M7 based CPU with 384 KB of Tightly Coupled Memory (TCM for data > and code) and 1MB of L2 SRAM. > The firmware this controller executes has to be loaded during boot-time of > the main CPU and can be any custom designed piece of firmware that serves > the needs of the application. In addition, the PSE can be a Zephyr OS based. > Sounds quite useful. Does Intel plan to do any of the following? - Release datasheets and register specs? - Add support to Zephyr OS upstream? - Release (open source) a reference application for PSE based on Zephyr OS? > > In order to perform the task in a given application, which might be e.g., > real-time communication over Time Sensitive Network (TSN), Intel(r) EC Lite > Service, Out Of Band (OOB) Management or even a network proxy, there are > several SoC internal peripherals that can be assigned to the PSE > (.../pci_devs.h [2]). This assignment must be done at boot time of the main > CPU and cannot be changed later. So once a peripheral is assigned to the > PSE, it disappears from the host subsystem and is only useable with the PSE > to perform the task in question. > There is one communication channel between the host subsystem and the PSE > subsystem so that the host CPU can communicate with the application running > on the PSE. IPC HW with HECI protocol. > There is further no way that the PSE application can access host dedicated > peripherals. To achieve this the PSE is equipped with a dedicated MMU which > isolates both subsystems. > > As mentioned earlier the Firmware of the PSE needs to be loaded at boot > time of the host CPU, this is mandatory for Elkhart Lake. There is a patch > on Gerrit provides an interface to load the PSE firmware > (soc/intel/elkhartlake: Introduce Intel PSE [1]. This patch does not > introduce the PSE-Firmware itself nor does it add a new blob to the > coreboot repository. In fact, this patch acquires the PSE firmware to load > located inside the CBFS and loads it into DRAM, adds some settings related > to the PSE like peripheral ownership and passes this DRAM buffer to the > FSP, which then performs the loading of the firmware among with the > settings into the PSE controller itself. > Is PSE required to boot? Or can it be disabled like ISH when it's not needed? > > > Please and thank you, > Sheng > > [1]: https://review.coreboot.org/c/coreboot/+/55367 > [2]: https://review.coreboot.org/c/coreboot/+/58466 > > _______________________________________________ > coreboot mailing list -- [email protected] > To unsubscribe send an email to [email protected] >
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