As Ron said, they are very useful. A lot of initialization happens before PCI is enabled. Bear in mind that the POST codes traditionally are written to IO port 0x80 (not PCI MMIO), so they can be output from firmware immediately after the CPU is let out of reset.
The old coreboot wiki has some information about POST codes and cards here: https://www.coreboot.org/POST_card On Mon, Jul 11, 2022 at 9:58 AM ron minnich <rminn...@gmail.com> wrote: > > They are incredibly useful, which is why they are still there. That > first post-bist code has been there since the first code in 1999. > > If you have jtag, it still helps. But many BMC also have ways to see > port 80 writes. You can see it before PCI is up. > > On Mon, Jul 11, 2022 at 8:00 AM Pedro Erencia <peren...@gmail.com> wrote: > > > > I've noticed that POST codes are sent very early. In x86 the first code is > > sent just after storing the bist. > > Are codes sent so early useful? They are sent ages before any PCI > > configuration. Is there any guarantee of them reaching a PCI POST card? > > _______________________________________________ > > coreboot mailing list -- coreboot@coreboot.org > > To unsubscribe send an email to coreboot-le...@coreboot.org > _______________________________________________ > coreboot mailing list -- coreboot@coreboot.org > To unsubscribe send an email to coreboot-le...@coreboot.org _______________________________________________ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-le...@coreboot.org
