Beware though that usually by default the I/O port 0x80 code aren't
routed to the PCI bus on any x86 platform that was released in maybe the
last maybe 10 years even if it still has PCI slots. The I/O port 0x80
writes often get decoded/routed to the LPC or eSPI bus on the platform
which is where the EC/SIO/BMC chip are connected to.
Regards,
Felix
On 11/07/2022 19:32, David Hendricks wrote:
As Ron said, they are very useful. A lot of initialization happens
before PCI is enabled. Bear in mind that the POST codes traditionally
are written to IO port 0x80 (not PCI MMIO), so they can be output from
firmware immediately after the CPU is let out of reset.
The old coreboot wiki has some information about POST codes and cards
here: https://www.coreboot.org/POST_card
On Mon, Jul 11, 2022 at 9:58 AM ron minnich <[email protected]> wrote:
They are incredibly useful, which is why they are still there. That
first post-bist code has been there since the first code in 1999.
If you have jtag, it still helps. But many BMC also have ways to see
port 80 writes. You can see it before PCI is up.
On Mon, Jul 11, 2022 at 8:00 AM Pedro Erencia <[email protected]> wrote:
I've noticed that POST codes are sent very early. In x86 the first code is sent
just after storing the bist.
Are codes sent so early useful? They are sent ages before any PCI
configuration. Is there any guarantee of them reaching a PCI POST card?
_______________________________________________
coreboot mailing list -- [email protected]
To unsubscribe send an email to [email protected]
_______________________________________________
coreboot mailing list -- [email protected]
To unsubscribe send an email to [email protected]
_______________________________________________
coreboot mailing list -- [email protected]
To unsubscribe send an email to [email protected]
_______________________________________________
coreboot mailing list -- [email protected]
To unsubscribe send an email to [email protected]
