Hi
MAX_ORDER is a memory management variable (in gpf.h – I think). If you grep for it you will find it. The MAX_ORDER defaults to 11 such that it limits how large a contiguous buffer can be allocated for. I’m not an expert (yet) on linux memory allocation and there are better ways to do this. Our application connects the TFP410 DVI encoder to the RGB, HSYNC, VSYNC, LCD_OE, and DCLK of the Davinci. The values I have listed below are default timings for XGA, tweaked slightly to get some of the 6446 signals to line up properly with the TFP410 -----Original Message----- From: Wu, Ruiyu (GE Healthcare) [mailto:[EMAIL PROTECTED] Sent: Thursday, November 16, 2006 10:21 PM To: Steve Spano Subject: 答复: ### LCD + DVI - Hopefully this will help others hi, Steve 1024x768, 60Hz 65.000 1024 24 136 160 768 3 6 29 hsync=135; hactive=1024; hfront=24; hback=160; vactive=768; vsync=20; vfront=3; vback=10; hint=hsync+hactive+100; // pad so we can slide the LCD_OE so we can make sure we catch all the CTL signals vint=vsync+vactive; hfront=hfront+hsync; then changed the MAX_ORDER variable in the memory management code (grep for MAX_ORDER) to 100. This is a bit of a hack, but its default is 11. This prevents allocation of contiguous buffers large enough to support 1024 x 768. what is the MAX_ORDER ?give me your LCD spec .I am confused with your lcd timing setting. and I don't use TFP 410 ,can you tell me the TFP 410 usage? -----邮件原件----- 发件人: Steve Spano [mailto:[EMAIL PROTECTED] 发送时间: 2006年11月15日 22:49 收件人: Wu, Ruiyu (GE Healthcare); [email protected] 主题: ### LCD + DVI - Hopefully this will help others Hi my issue apparently revolved around KEY undocumented registers. What we did is connect the TI TFP410 to the VSYNC, LCD_OE, HSYNC, PCLK, and RGB888 outputs from the davinci. The PINMUX0 and PINMUX1 registers need to be setup to enable RGB888 AND LCD_OE Mode. I changed the X and Y resolution in davincifb.c to 1024 x 768 I then changed the MAX_ORDER variable in the memory management code (grep for MAX_ORDER) to 100. This is a bit of a hack, but its default is 11. This prevents allocation of contiguous buffers large enough to support 1024 x 768 Then, introduced the following function to enable RGB888 at 1024 x 768 using a 65MHz clock static void davincifb_rgb_config(int on) { DBGENTER; char data[10]; char temp[20]; unsigned int hsync,hactive,hfront,hback; unsigned int vsync,vactive,vfront,vback; unsigned int hint,vint; int notfound=1; memset(temp,0,sizeof(temp)); memset(data,0,sizeof(data)); printk("** Configuring for RGB Video Mode\r\n"); if (on) { /* Reset video encoder module */ dispc_reg_out(VENC_VMOD, 0); dispc_reg_out(VENC_VMOD,0x2013); // start video encoder in RGB mode dispc_reg_out(VENC_VIDCTL,0x2000); // enable video clock output dispc_reg_out(VENC_SYNCCTL,0x000F); // hsync + vsync are on active low polarity // undocumented registers. They are actually 'barely' //documented. The docs sort of explain them, but Hiroshi actually made it //work dispc_reg_out(VENC_DCLKCTL,0x0800); dispc_reg_out(VENC_DCLKPTN0,0x0001); dispc_reg_out(VPSS_CLKCTL,0x0009); // generate 63MHz DCLK dispc_reg_out(VPSS_PLLDIV1,0x0009); dispc_reg_out(VPSS_PLLDIV1,0x8009); /* // standard video modes CLK 640x480, 60Hz 25.175 640 16 96 48 480 11 2 31 640x480, 72Hz 31.500 640 24 40 128 480 9 3 28 640x480, 75Hz 31.500 640 16 96 48 480 11 2 32 640x480, 85Hz 36.000 640 32 48 112 480 1 3 25 800x600, 56Hz 38.100 800 32 128 128 600 1 4 14 800x600, 60Hz 40.000 800 40 128 88 600 1 4 23 800x600, 72Hz 50.000 800 56 120 64 600 37 6 23 800x600, 75Hz 49.500 800 16 80 160 600 1 2 21 800x600, 85Hz 56.250 800 32 64 152 600 1 3 27 1024x768, 60Hz 65.000 1024 24 136 160 768 3 6 29 1024x768, 70Hz 75.000 1024 24 136 144 768 3 6 29 */ // horizontal sync pulse width hsync=135; hactive=1024; hfront=24; hback=160; vactive=768; vsync=20; vfront=3; vback=10; hint=hsync+hactive+100; // pad so we can slide the LCD_OE so we can make sure we catch all the CTL signals vint=vsync+vactive; hfront=hfront+hsync; dispc_reg_out(VENC_HSPLS,hsync); dispc_reg_out(VENC_HINT,hint); dispc_reg_out(VENC_HSTART,hfront); dispc_reg_out(VENC_HVALID,hactive); dispc_reg_out(VENC_VSPLS,vsync); dispc_reg_out(VENC_VINT,vint); dispc_reg_out(VENC_VSTART,vfront); dispc_reg_out(VENC_VVALID,vactive); dispc_reg_out(VENC_HSDLY,0); dispc_reg_out(VENC_VSDLY,0); // crazy part#1000 // these registers are barely documented but they are // key to keeping the OSD module and the VENC module synced // set these bits to basically NOT-GATE the OSD clock // Why is this BARELY documented - its so key!!! dispc_reg_out(VENC_OSDCLK0,0xffff); dispc_reg_out(VENC_OSDCLK1,0xffff); dispc_reg_out(VENC_OSDHAD,50); // advance the timing? why not // dont cull anything! dispc_reg_out(VENC_HVLDCL0,0xffffffff); dispc_reg_out(VENC_HVLDCL1,0xffffffff); dispc_reg_out(VENC_LCDOUT,0x0001); // enable LCD_OE to active high dispc_reg_out(VENC_RGBCTL,0); // stadnard RGB output printk ("Seeking TFP410 DVI Encoder....\r\n"); // get device ID register data[0]=0x00; davinci_i2c_write (1, data, TFP410); davinci_i2c_read (2, temp, TFP410); printk("*** Device ID = 0x%02x%02x\r\n",temp[0],temp[1]); if (temp[0]==0x10 && temp[1]==0x04) { printk("Located TFP410....\r\n"); notfound=0; } else { printk("TFP410 not found...critical fault....\r\n"); // while(1) // { // } } printk("Configuring TFP410 Interface device\r\n"); data[0]=0x08; // select CTL_1 data[1]=0x07; davinci_i2c_write (2, data, TFP410); // generate color bars // dispc_reg_out(VENC_VDPRO,0x0100); } else { /* Reset video encoder module */ dispc_reg_out(VENC_VMOD, 0); } DBGEXIT; }
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