I believe the references to using the 54MHz clock to drive the VENC are to
allow proper operation of the NTSC\PAL encoding logic. Using the 54MHz clock
input allows for proper operation at standard video rates. However, our
system is driving only using the parallel RGB888 outputs to drive a 1024x768
LCD. So, I configured the VENC to use non-standard timing and generated a
pixel clock of ~72MHz using the PLL2. Below is a code snippet showing my
configuration (Note: I am not working in linux, this code is from my own
standalone setup code but it should be readable enough to get the point
across).
pReg = (DVReg32 *)VPSS_CLKCTL;
*pReg = VPSS_DACCLKEN | VPSS_VENCLKEN | VPSS_MUXSEL_PLL2;
// Set burst priority
pReg = (DVReg32 *)DDR2_PBBPR;
*pReg = 0x7F;
// Configure for RBG888 output
pReg = (DVReg32 *)DAVINCI_PINMUX0_REG;
*pReg = (*pReg | PINMUX0_LOEEN | PINMUX0_RGB888) &
~(PINMUX0_CFLDEN | PINMUX0_CWEN | PINMUX0_LFLDEN);
pReg = (DVReg32 *)DAVINCI_PINMUX1_REG;
*pReg &= ~(PINMUX1_PWM2 | PINMUX1_PWM1);
// Set clock divisor
vpbe->PCR = 0;
// Turn off venc and osd
venc->VMOD &= ~VENC_VMOD_VENC_ENABLE;
osd->VIDWINMD &=~(OSD_VIDWINMD_ACT1 | OSD_VIDWINMD_ACT0);
osd->OSDWIN0MD &= ~OSD_OSDWIN0MD_OACT;
osd->OSDWIN1MD &= ~OSD_OSDWIN1MD_OACT;
vpss->PCR = 0x0;
// Set up timing for LCD
venc->VIDCTL = VENC_VIDCTL_VCLKP | VENC_VIDCTL_VCLKE;
venc->SYNCCTL = VENC_SYNCCTL_VPL | VENC_SYNCCTL_HPL | VENC_SYNCCTL_SYEH |
VENC_SYNCCTL_SYEV;
venc->HSPLS = pLCD->Horiz.Sync;
venc->HSTART = pLCD->Horiz.Start;
venc->HVALID = pLCD->Horiz.Valid;
venc->HINT = pLCD->Horiz.Interval;
venc->VSPLS = pLCD->Vert.Sync;
venc->VSTART = pLCD->Vert.Start;
venc->VVALID = pLCD->Vert.Valid;
venc->VINT = pLCD->Vert.Interval;
venc->LCDOUT = VENC_LCDOUT_OEE;
venc->OSDCLK0 = 0;
venc->OSDCLK1 = 1;
venc->DCLKCTL = 0x0800;
venc->DCLKPTN0 = 0x0001;
venc->VMOD |= VENC_VMOD_VDMD_PRGB | VENC_VMOD_NON_NTSCPAL |
VENC_VMOD_VENC_ENABLE;
venc->YCCTL = 0x0001;
osd->MODE = 0x0000;
osd->VIDWINMD = 0x0000;
osd->VIDWIN0OFST = (3 * pLCD->Horiz.Valid) / 32;
osd->VIDWIN0ADR = TheExtension.VideoBuffer[0];
osd->BASEPX = pLCD->Horiz.Start;
osd->BASEPY = pLCD->Vert.Start;
osd->VIDWIN0XP = 0;
osd->VIDWIN0YP = 0;
osd->VIDWIN0XL = pLCD->Horiz.Valid;
osd->VIDWIN0YL = pLCD->Vert.Valid;
osd->MISCCTL = OSD_MISCCTL_RGBEN;
osd->PPVWIN0ADR = TheExtension.VideoBuffer[1];
osd->VIDWINMD = OSD_VIDWINMD_ACT0;
venc->DACTST = 0x0000;
-----Original Message-----
Message: 1
Date: Tue, 28 Nov 2006 18:45:25 +0100
From: Lorenzo Lutti <[EMAIL PROTECTED]>
Subject: Re: Davinci-linux-open-source Digest, Vol 11, Issue 77
To: davinci-linux-open-source
<[email protected]>
Message-ID: <[EMAIL PROTECTED]>
Content-Type: text/plain; charset=ISO-8859-15; format=flowed
Anthony P. Lannutti ha scritto:
> When I was working on attaching an LCD to the DVEVM I had the same
> questions. Attached are 2 PDF files with as much explanation as I was able
> to get.
Thank you so much, this will help me a lot! Since you already did this, did
you work also on the clock generator for the VENC? SPRUE37 isn't overly
clear on that, it seems that you basically are forced to use a 54 MHz clock
if you want to use the PLL2 input; instead, if you look at SPRUE14
(paragraph 3.1 and following), it looks like this frequency is easily
programmable through the PLL2 divisors; well, apparently table 6-2 contains
some contaddictory data, but probably it's just a typo.
I basically need a pixel frequency comprised from 4.62 and 6.04 MHz, and my
options are basically two:
1) MUXSEL=2: generate an external frequency of 10.66 MHz, feed it to the
VPBECLK input and use VENC_DIV2 (I can't feed VPBECLK with 5.33 MHz because
it's out of its range);
2) MUXSEL=1: use PLL2 to generate the frequency accordingly. With the DVEVM
defaults, the PLL2 frequency is 27*14=378 MHz, therefore I would need to
divide it by 32 (the maximum PLLDIV1 divider value) and then use VENC_DIV2,
and I will get 5.9 MHz. Maybe :)
> I believe the DCLKCTL.pdf is an excerpt from a new version of the
> Video Processing Back End (VPBE) User's Guide (sprue37.pdf) and the other
is
> pages 57-61 of the TMS320DM6446 datasheet (sprs283c.pdf) showing the
> VPSS_CLK_CTRL register description.
Now I understand why I wasn't able to find that paragraph: in the version
currently available on TI site (SPRUE283D, revised in september 2006) is has
been removed! I wonder why.
Thank you again!
Cheers, Lorenzo
_______________________________________________
Davinci-linux-open-source mailing list
[email protected]
http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source
