Anthony P. Lannutti ha scritto:
When I was working on attaching an LCD to the DVEVM I had the same questions. Attached are 2 PDF files with as much explanation as I was able to get.
Thank you so much, this will help me a lot! Since you already did this, did you work also on the clock generator for the VENC? SPRUE37 isn't overly clear on that, it seems that you basically are forced to use a 54 MHz clock if you want to use the PLL2 input; instead, if you look at SPRUE14 (paragraph 3.1 and following), it looks like this frequency is easily programmable through the PLL2 divisors; well, apparently table 6-2 contains some contaddictory data, but probably it's just a typo. I basically need a pixel frequency comprised from 4.62 and 6.04 MHz, and my options are basically two: 1) MUXSEL=2: generate an external frequency of 10.66 MHz, feed it to the VPBECLK input and use VENC_DIV2 (I can't feed VPBECLK with 5.33 MHz because it's out of its range); 2) MUXSEL=1: use PLL2 to generate the frequency accordingly. With the DVEVM defaults, the PLL2 frequency is 27*14=378 MHz, therefore I would need to divide it by 32 (the maximum PLLDIV1 divider value) and then use VENC_DIV2, and I will get 5.9 MHz. Maybe :)
I believe the DCLKCTL.pdf is an excerpt from a new version of the Video Processing Back End (VPBE) User's Guide (sprue37.pdf) and the other is pages 57-61 of the TMS320DM6446 datasheet (sprs283c.pdf) showing the VPSS_CLK_CTRL register description.
Now I understand why I wasn't able to find that paragraph: in the version currently available on TI site (SPRUE283D, revised in september 2006) is has been removed! I wonder why. Thank you again! Cheers, Lorenzo _______________________________________________ Davinci-linux-open-source mailing list [email protected] http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source
