Lorenzo Lutti ha scritto:
2) MUXSEL=1: use PLL2 to generate the frequency accordingly. With the DVEVM defaults, the PLL2 frequency is 27*14=378 MHz, therefore I would need to divide it by 32 (the maximum PLLDIV1 divider value) and then use VENC_DIV2, and I will get 5.9 MHz. Maybe :)
I'm starting to see some signal going, but there's a thing I don't understand: while SPRUE14 states that the PLLDIVx registers RATIO range is 00-1F (divide from 1 to 32), the value written to the registers (for example PLL2.PLLDIV1) is truncated to the first four bits, thus the allowed ratio is 1-16. Is this by design, is this a silicon bug (not reported in the last errata) or do I have to enable something else to use the ratios from 17 to 32? Cheers, Lorenzo P.S. BTW, I've noticed that sometimes my messages don't get published on this list. It's just a problem of my outgoing mail server or does this happen to something else? _______________________________________________ Davinci-linux-open-source mailing list [email protected] http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source
