Lorenzo Lutti ha scritto:
I'm starting to see some signal going, but there's a thing I don't understand: while SPRUE14 states that the PLLDIVx registers RATIO range is 00-1F (divide from 1 to 32), the value written to the registers (for example PLL2.PLLDIV1) is truncated to the first four bits, thus the allowed ratio is 1-16. Is this by design, is this a silicon bug (not reported in the last errata) or do I have to enable something else to use the ratios from 17 to 32?
Maybe this information could be useful to someone: TI confirmed that in fact PLL2 PLLDIV1 range is just 0..0xF, not 0..0x1F like sprue14 says. They will fix the documentation in the next release. Cheers, Lorenzo _______________________________________________ Davinci-linux-open-source mailing list [email protected] http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source
