________________________________
From: Andy Ngo [mailto:[EMAIL PROTECTED]
Sent: Friday, March 02, 2007 2:45 AM
To: Gary, Scott; Adam Dawidziuk
Cc: davinci-linux-open-source @linux.davincidsp.com
Subject: Re: Cache coherency issue?
Nope, that didn't help. I tried allocating 1024 bytes for the
output buffer (I only needed 105 bytes as stated
in my previous email) and I still have the stale data problem
unless I explicitly do a writeback
invalidate. So that eliminates the "integral number of cache
lines" requirement as the culprit
for my cache problem. I used Memory_contigAlloc so that should
take care of the contiguous
requirement, how do you ensure the cache-line alignment
requirement?
Andy,
If you are using Memory_contigAlloc, then alignment will be handled
automatically too.
Also, one correction to what I wrote earlier regarding trace: the
environment variable you should set is not CE_TRACE (this controls
ARM-side trace), but should be TRACEUTIL_DSP0TRACEMASK. If you've not
used TraceUtil before, this is described in section 4.6 of SPRUE67,
Codec Engine Application Developer User's Guide.
The trace info will show what the skeletons are doing, to compare to
your explicit call to writeback invalidate...
Regards,
Scott
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