Andy,
I'm guessing that the ACFG2 register is not set because the Platform.S is executing from the CS2 memory region. You don't want to modify the timing information in the middle of accesses to that region. The defaults for the registers are set to provide the maximum delays to be the most compatible with even the slowest attached device. It's simple, but you are right, it's not the fastest. You probably should be able to tailor the values written there for your specific device (as long as you don't exceed the specs of your NOR device). Let us know how it goes. Regards, Daniel Daniel J. Allred Software Applications Catalog DSP / Emerging End Equipment ________________________________ From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED] On Behalf Of Andy Ngo Sent: Wednesday, March 28, 2007 2:27 PM To: davinci-linux-open-source @linux.davincidsp.com Subject: NOR flash asynchronous configuration register settings Hi, In trying to figure what ACR value to used for the Spansion NOR flash on our custom Davinci board, I planned to use the settings on the DVEVM board as a guide. However, when I looked at the ACR settings (ACFG2-5) in board/davinci/platform.S in u-boot, I see ACFG2 (AMD NOR flash is hooked up to CS2 on the AEMIF) is not initialized at all, on ACFG3-5 are initialized (and they all have a value of 0x3FFFFFFD). So I tried looking at the gel file (DaVinciEVM_arm.gel) that gets launched when CCS 3.2 starts and it does initialize ACFG2 in addition to ACFG3-5; but again, all the values are set to 0x3FFFFFFD (maximum time out). 1) Why isn't ACFG2 initialized in platform.S? 2) Why are the ACFGx values all set to 0x3FFFFFFD? Won't this make accesses to the NOR flash or any AEMIF memory device very slow? Thanks. Regards, Andy
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