Source: Texas Instruments Inc. Type: Enhancement Signed-off-by: Sudhakar Rajashekhara <[EMAIL PROTECTED]> Description: This patch defines the base addresses and LPSC assignments for DM6467. --- include/asm-arm/arch-davinci/hardware.h | 73 +++++++++++++++++++++++++++++++ 1 files changed, 73 insertions(+), 0 deletions(-)
diff --git a/include/asm-arm/arch-davinci/hardware.h b/include/asm-arm/arch-davinci/hardware.h index a2e8969..bca3d7a 100644 --- a/include/asm-arm/arch-davinci/hardware.h +++ b/include/asm-arm/arch-davinci/hardware.h @@ -49,4 +49,77 @@ #define DAVINCI_ASYNC_EMIF_DATA_CE3_BASE (0x08000000) #define DAVINCI_VLYNQ_REMOTE_BASE (0x0C000000) +#define DM644X_UART2_BASE (0x01C20800) +#define DM644X_ASYNC_EMIF_CNTRL_BASE (0x01E00000) +#define DM644X_DDR2_CNTL_BASE (0x20000000) + +/* + * DM6467 base register addresses different from original DaVinci + */ +#define DAVINCI_DM646X_DMA_3PTC2_BASE (0x01C10800) +#define DAVINCI_DM646X_DMA_3PTC3_BASE (0x01C10C00) +#define DAVINCI_DM646X_VIDEO_PORT_BASE (0x01C12000) +#define DAVINCI_DM646X_VDCE_BASE (0x01C12800) +#define DAVINCI_DM646X_TSIF0_BASE (0x01C13000) +#define DAVINCI_DM646X_TSIF1_BASE (0x01C13400) +#define DAVINCI_DM646X_PCI_CTL_BASE (0x01C1A000) +#define DAVINCI_DM646X_CRGEN0_BASE (0x01C26000) +#define DAVINCI_DM646X_CRGEN1_BASE (0x01C26400) +#define DAVINCI_DM646X_SEC_CONTROLLER_BASE (0x01C40400) +#define DAVINCI_DM646X_MCASP0_REG_BASE (0x01D01000) +#define DAVINCI_DM646X_MCASP0_DATA_PORT_BASE (0x01D01400) +#define DAVINCI_DM646X_MCASP1_REG_BASE (0x01D01800) +#define DAVINCI_DM646X_MCASP1_DATA_PORT_BASE (0x01D01C00) +#define DAVINCI_DM646X_HDVICP0_BASE (0x02000000) +#define DAVINCI_DM646X_HDVICP1_BASE (0x02200000) +#define DAVINCI_DM646X_ASYNC_EMIF_CNTRL_BASE (0x20008000) +#define DAVINCI_DM646X_VLYNQ_BASE (0x20010000) +#define DAVINCI_DM646X_ASYNC_EMIF_DATA_CE0_BASE (0x42000000) +#define DAVINCI_DM646X_ASYNC_EMIF_DATA_CE1_BASE (0x44000000) +#define DAVINCI_DM646X_ASYNC_EMIF_DATA_CE2_BASE (0x46000000) +#define DAVINCI_DM646X_ASYNC_EMIF_DATA_CE3_BASE (0x48000000) +#define DAVINCI_DM646X_VLYNQ_REMOTE_BASE (0x4C000000) + +/* + * LPSC Assignments + */ +#define DAVINCI_DM646X_LPSC_RESERVED 0 +#define DAVINCI_DM646X_LPSC_C64X_CPU 1 +#define DAVINCI_DM646X_LPSC_HDVICP0 2 +#define DAVINCI_DM646X_LPSC_HDVICP1 3 +#define DAVINCI_DM646X_LPSC_TPCC 4 +#define DAVINCI_DM646X_LPSC_TPTC0 5 +#define DAVINCI_DM646X_LPSC_TPTC1 6 +#define DAVINCI_DM646X_LPSC_TPTC2 7 +#define DAVINCI_DM646X_LPSC_TPTC3 8 +#define DAVINCI_DM646X_LPSC_PCI 13 +#define DAVINCI_DM646X_LPSC_EMAC 14 +#define DAVINCI_DM646X_LPSC_VDCE 15 +#define DAVINCI_DM646X_LPSC_VPSSMSTR 16 +#define DAVINCI_DM646X_LPSC_VPSSSLV 17 +#define DAVINCI_DM646X_LPSC_TSIF0 18 +#define DAVINCI_DM646X_LPSC_TSIF1 19 +#define DAVINCI_DM646X_LPSC_DDR_EMIF 20 +#define DAVINCI_DM646X_LPSC_AEMIF 21 +#define DAVINCI_DM646X_LPSC_McASP0 22 +#define DAVINCI_DM646X_LPSC_McASP1 23 +#define DAVINCI_DM646X_LPSC_CRGEN0 24 +#define DAVINCI_DM646X_LPSC_CRGEN1 25 +#define DAVINCI_DM646X_LPSC_UART0 26 +#define DAVINCI_DM646X_LPSC_UART1 27 +#define DAVINCI_DM646X_LPSC_UART2 28 +#define DAVINCI_DM646X_LPSC_PWM0 29 +#define DAVINCI_DM646X_LPSC_PWM1 30 +#define DAVINCI_DM646X_LPSC_I2C 31 +#define DAVINCI_DM646X_LPSC_SPI 32 +#define DAVINCI_DM646X_LPSC_GPIO 33 +#define DAVINCI_DM646X_LPSC_TIMER0 34 +#define DAVINCI_DM646X_LPSC_TIMER1 35 +#define DAVINCI_DM646X_LPSC_ARM_INTC 45 + +/* + * Macro to access device power control + */ +#define DAVINCI_VDD3P3V_PWDN (DAVINCI_SYSTEM_MODULE_BASE + 0x48) + #endif /* __ASM_ARCH_HARDWARE_H */ -- 1.5.4.1 _______________________________________________ Davinci-linux-open-source mailing list [email protected] http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source
