Hi Tim, I have worked on similar situation but the SPI interface is between two DM6467 platform. one DM6467 will be working as Master and another DM6467 as Slave. The below link may help you to resolve your problem. http://linux.omap.com/pipermail/davinci-linux-open-source/2007-December/0048 36.html <http://linux.omap.com/pipermail/davinci-linux-open-source/2007-December/004 836.html> Regards, Suresh S
-----Original Message----- From: [EMAIL PROTECTED] om [mailto:[EMAIL PROTECTED] ncidsp.com]On Behalf Of Xu, Li (GE, Research) Sent: Wednesday, October 15, 2008 12:08 PM To: [email protected] Cc: Xu, Li (GE, Research) Subject: DaVinci SPI read and write Dear DaVinci Folks, I recently working on SPI interface in DM6446 and DM6467 platform. DM6446 is configured as master, whereas DM6467 as slave, both working in interrupt mode. I can see clock and data signal via oscilloscope when DM6446 sending data via SPI interface, but I am not able to receive any data at DM6467 side. However, the interrupt service routine in DM6467 side is activated when DM6446 sending data, but SPI Flag Status Register (SPIFLG) does not indicate any valid interrupt has occured, the value of this register is 0x800000, according to data sheet, 31-10 bit of this register is reserved, reads should return zero. I was very confused about what I get right now. Does anyone have similar situation as me? Your response will be highly appreciated. For your information, the SPI driver I am using contains below files: spi-core.c spi_davinci.c spi_davinci_client.c spi_davinci_lb_test.c spi-dev.c Regards Tim The information contained in this electronic message and any attachments to this message are intended for the exclusive use of the addressee(s) and may contain proprietary, confidential or privileged information. If you are not the intended recipient, you should not disseminate, distribute or copy this e-mail. Please notify the sender immediately and destroy all copies of this message and any attachments contained in it.
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