Tom,
I don't think I quite understand what you are proposing, but at first
glance it doesn't seem plausible. NAND does not behave like a NOR flash in
terms of how you read from it. NOR is similar to SRAM in the sense that you
supply an address and control signals and data is presented. NAND on the other
hand, uses a sequence of cycles to perform a series of reads. There is a
command, address and then data cycles.
Perhaps I have misinterpreted what you are trying to do. If it is to
connect an 8-bit NAND on the lower 8-bits of the processor data bus and another
8-bit NAND on the upper 8-bits of the processor data bus, then this will not
work, especially during boot. Even if the booting process was somehow solved,
I don't think the software driver for this arrangement would be very elegant.
Brandon Azbell
Texas Instruments
________________________________
From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED] On Behalf Of Tom Briggs
Sent: Friday, October 24, 2008 12:39 PM
To: [email protected]
Subject: NAND question
We are interested in improving the performance of our NAND reads by using two
8-bit banks of NAND chips and using EMIFA in 16-bit addressing mode. Has
anyone done this, or know of any problems this may have, specifically using
UBoot and/or Linux?
-tom
--
--------------------------------------------------------
Tom Briggs
Assistant Professor
Department of Computer Science
[EMAIL PROTECTED]
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