From: Naresh Medisetty <[email protected]> Enables the module clock for EDMA channel controller and transfer controller. Maps channels to param sets which is specific to dm646x. Registers the error handlers for the transfer controllers (tc2 and tc3).
Signed-off-by: Naresh Medisetty <[email protected]> --- arch/arm/mach-davinci/dm646x.c | 40 +++++++++++++++++++++++ arch/arm/mach-davinci/dma.c | 49 ++++++++++++++++++++++++++++- arch/arm/mach-davinci/include/mach/edma.h | 10 ++++++ 3 files changed, 98 insertions(+), 1 deletions(-) diff --git a/arch/arm/mach-davinci/dm646x.c b/arch/arm/mach-davinci/dm646x.c index 0bdc397..ec8ef70 100644 --- a/arch/arm/mach-davinci/dm646x.c +++ b/arch/arm/mach-davinci/dm646x.c @@ -155,6 +155,41 @@ static struct clk arm_clk = { .flags = ALWAYS_ENABLED, }; +static struct clk edma_cc_clk = { + .name = "edma_cc", + .parent = &pll1_sysclk2, + .lpsc = DM646X_LPSC_TPCC, + .flags = ALWAYS_ENABLED, +}; + +static struct clk edma_tc0_clk = { + .name = "edma_tc0", + .parent = &pll1_sysclk2, + .lpsc = DM646X_LPSC_TPTC0, + .flags = ALWAYS_ENABLED, +}; + +static struct clk edma_tc1_clk = { + .name = "edma_tc1", + .parent = &pll1_sysclk2, + .lpsc = DM646X_LPSC_TPTC1, + .flags = ALWAYS_ENABLED, +}; + +static struct clk edma_tc2_clk = { + .name = "edma_tc2", + .parent = &pll1_sysclk2, + .lpsc = DM646X_LPSC_TPTC2, + .flags = ALWAYS_ENABLED, +}; + +static struct clk edma_tc3_clk = { + .name = "edma_tc3", + .parent = &pll1_sysclk2, + .lpsc = DM646X_LPSC_TPTC3, + .flags = ALWAYS_ENABLED, +}; + static struct clk uart0_clk = { .name = "uart0", .parent = &aux_clkin, @@ -248,6 +283,11 @@ struct davinci_clk dm646x_clks[] = { CLK(NULL, "pll2_sysclk1", &pll2_sysclk1), CLK(NULL, "dsp", &dsp_clk), CLK(NULL, "arm", &arm_clk), + CLK(NULL, "edma_cc", &edma_cc_clk), + CLK(NULL, "edma_tc0", &edma_tc0_clk), + CLK(NULL, "edma_tc1", &edma_tc1_clk), + CLK(NULL, "edma_tc2", &edma_tc2_clk), + CLK(NULL, "edma_tc3", &edma_tc3_clk), CLK(NULL, "uart0", &uart0_clk), CLK(NULL, "uart1", &uart1_clk), CLK(NULL, "uart2", &uart2_clk), diff --git a/arch/arm/mach-davinci/dma.c b/arch/arm/mach-davinci/dma.c index 575f13c..4b9972f 100644 --- a/arch/arm/mach-davinci/dma.c +++ b/arch/arm/mach-davinci/dma.c @@ -102,6 +102,12 @@ #define PARM_OFFSET(param_no) (EDMA_PARM + ((param_no) << 5)) +/* dm646x specific */ +#define EDMA_DCHMAP 0x0100 /* 64 registers */ + + + + #define EDMA_MAX_DMACH 64 #define EDMA_MAX_PARAMENTRY 512 @@ -258,6 +264,14 @@ static void __init assign_priority_to_queue(int queue_no, int priority) edma_modify(EDMA_QUEPRI, ~(0x7 << bit), ((priority & 0x7) << bit)); } +/* dm646x specific */ +static void __init map_dm646x_dmach_param() +{ + int i; + for (i = 0; i < EDMA_MAX_DMACH; i++) + edma_write_array(EDMA_DCHMAP , i , (i << 5)); +} + static inline void setup_dma_interrupt(unsigned lch, void (*callback)(unsigned channel, u16 ch_status, void *data), @@ -427,6 +441,20 @@ static irqreturn_t dma_tc1err_handler(int irq, void *data) return IRQ_HANDLED; } +/* dm646x specific */ +static irqreturn_t dma_tc2err_handler(int irq, void *data) +{ + dev_dbg(data, "dma_tc2err_handler\n"); + return IRQ_HANDLED; +} + +static irqreturn_t dma_tc3err_handler(int irq, void *data) +{ + dev_dbg(data, "dma_tc3err_handler\n"); + return IRQ_HANDLED; +} + + /*-----------------------------------------------------------------------*/ /* Resource alloc/free: dma channels, parameter RAM slots */ @@ -1052,6 +1080,22 @@ static int __init edma_probe(struct platform_device *pdev) IRQ_TCERRINT, status); return status; } + if (cpu_is_davinci_dm646x()) { + status = request_irq(IRQ_DM646X_TCERRINT2, + dma_tc2err_handler, 0, "edma_tc2", NULL); + if (status < 0) { + dev_dbg(&pdev->dev, "request_irq %d failed-->%d\n" + , IRQ_DM646X_TCERRINT2, status); + return status; + } + status = request_irq(IRQ_DM646X_TCERRINT3, + dma_tc3err_handler, 0, "edma_tc3", NULL); + if (status < 0) { + dev_dbg(&pdev->dev, "request_irq %d --> %d\n", + IRQ_DM646X_TCERRINT3, status); + return status; + } + } } /* Everything lives on transfer controller 1 until otherwise specified. @@ -1063,7 +1107,6 @@ static int __init edma_probe(struct platform_device *pdev) queue_tc_mapping = info->queue_tc_mapping; queue_priority_mapping = info->queue_priority_mapping; - /* Event queue to TC mapping */ for (i = 0; queue_tc_mapping[i][0] != -1; i++) map_queue_tc(queue_tc_mapping[i][0], queue_tc_mapping[i][1]); @@ -1073,6 +1116,10 @@ static int __init edma_probe(struct platform_device *pdev) assign_priority_to_queue(queue_priority_mapping[i][0], queue_priority_mapping[i][1]); + if (cpu_is_davinci_dm646x()) + map_dm646x_dmach_param(); + + for (i = 0; i < info->n_region; i++) { edma_write_array2(EDMA_DRAE, i, 0, 0x0); edma_write_array2(EDMA_DRAE, i, 1, 0x0); diff --git a/arch/arm/mach-davinci/include/mach/edma.h b/arch/arm/mach-davinci/include/mach/edma.h index 8a80a9e..4628c75 100644 --- a/arch/arm/mach-davinci/include/mach/edma.h +++ b/arch/arm/mach-davinci/include/mach/edma.h @@ -74,6 +74,9 @@ struct edmacc_param { #define CCERRINT_INTERRUPT 17 #define TCERRINT0_INTERRUPT 18 #define TCERRINT1_INTERRUPT 19 +/* dm646x specific */ +#define TCERRINT2_INTERRUPT 20 +#define TCERRINT3_INTERRUPT 21 #define EDMA_MAX_EVQUE 2 /* FIXME too small */ /* dm646x specific */ @@ -149,6 +152,11 @@ struct edmacc_param { #define DMA_CC_ERROR 2 #define DMA_TC1_ERROR 3 #define DMA_TC2_ERROR 4 +/* dm646x specific */ +#define DMA_TC3_ERROR 5 +#define DMA_TC4_ERROR 6 + + enum address_mode { INCR = 0, @@ -167,6 +175,8 @@ enum fifo_width { enum dma_event_q { EVENTQ_0 = 0, EVENTQ_1 = 1, + EVENTQ_2 = 2, + EVENTQ_3 = 3, EVENTQ_DEFAULT = -1 }; -- 1.5.6 _______________________________________________ Davinci-linux-open-source mailing list [email protected] http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source
