After a bit more debugging on the GPIO interrupt issues, I think there is a fundamental hardware limitation in having flexibility of using GPIO bank interrupts and direct interrupts at the same time.
In order to configure a GPIO as an interrupt (either banked or direct), you have to set the edge-detection mode via the [SET|CLR]_RIS_TRIG, [SET|CLR]_FAL_TRIG registers. Setting these also has the side effect of enabling/disabling the interrupt. The catch is that this enables the *both* the direct interrupt and the banked interrupt and there appears to be no way to enable them independently. The only way to prevent both interrupts from firing (and causing two handlers to run) is to mask one of them at the AINTC. Of course, masking the banked interrupt at the AINTC means you mask all GPIOs in that bank. So, within a given bank, it's not practical to use a mixture of direct and banked interrupts as they could not be individually masked on a per-GPIO basis. On dm646x, dm355 and dm646x, this is really only problematic for GPIO bank 0 where there are GPIOs that can be configured both ways. Essentially, the non-direct mapped GPIOs in bank 0 become pretty useless. On dm365, there appear to be only direct interrupts, and on omap-l1x, a quick glance at the interrupt table suggests that there are only banked interrupts. Both of those will be simpler to handle then when both are present. I guess I need to think about how better to extend the current GPIO code to be able to handle both cleanly. Kevin _______________________________________________ Davinci-linux-open-source mailing list [email protected] http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source
