On Monday 11 May 2009, Kevin Hilman wrote:
> > Seems like the notion for now is to make at least dm355 use direct
> > mapped IRQs on bank 0?
>
> Well, if the banked interrupts can work, I think it's simpler to just
> use banked interrupts or everything.
That was my thought. They basically work ... except for whatever
this issue is which afflicts the dm9000. Plus, they are documented
to have some triggering controls, which AINTC-only IRQs don't.
> But I still don't understand
> understand why the banked interrupt is not working like the direct
> mapped interrupt for the dm9000.
Right. When you experimented, did you disable BINTEN for bank 0?
p.s. Appended is a not-quite-working-right update to let gpio
banks configure themselves to use direct IRQs. On the
dm355evm the dm9000 is behaving as before, but the msp430
irqs weren't arriving.
---
arch/arm/mach-davinci/gpio.c | 28 ++++++++++++++++++++++++++--
arch/arm/mach-davinci/include/mach/gpio.h | 14 ++------------
2 files changed, 28 insertions(+), 14 deletions(-)
--- a/arch/arm/mach-davinci/gpio.c
+++ b/arch/arm/mach-davinci/gpio.c
@@ -34,6 +34,8 @@ static DEFINE_SPINLOCK(gpio_lock);
struct davinci_gpio {
struct gpio_chip chip;
struct gpio_controller *__iomem regs;
+ unsigned irqbase;
+ int nirq;
};
static struct davinci_gpio chips[DIV_ROUND_UP(DAVINCI_N_GPIO, 32)];
@@ -111,6 +113,15 @@ davinci_gpio_set(struct gpio_chip *chip,
__raw_writel((1 << offset), value ? &g->set_data : &g->clr_data);
}
+static int davinci_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
+{
+ struct davinci_gpio *d = container_of(chip, struct davinci_gpio, chip);
+
+ if (offset >= d->nirq)
+ return -EINVAL;
+ return d->irqbase + offset;
+}
+
static int __init davinci_gpio_setup(void)
{
int i, base;
@@ -144,6 +155,9 @@ static int __init davinci_gpio_setup(voi
if (chips[i].chip.ngpio > 32)
chips[i].chip.ngpio = 32;
+ chips[i].chip.to_irq = davinci_gpio_to_irq;
+ chips[i].nirq = -1;
+
chips[i].regs = gpio2controller(base);
gpiochip_add(&chips[i].chip);
@@ -289,15 +303,24 @@ static int __init davinci_gpio_irq_setup
}
clk_enable(clk);
- for (gpio = 0, irq = gpio_to_irq(0), bank = 0;
+ for (gpio = 0, irq = soc_info->intc_irq_num, bank = 0;
gpio < ngpio;
bank++, bank_irq++) {
struct gpio_controller *__iomem g = gpio2controller(gpio);
unsigned i;
+ unsigned gpiobank = bank >> 1;
__raw_writel(~0, &g->clr_falling);
__raw_writel(~0, &g->clr_rising);
+ /* set up gpio->irq mapping first time through;
+ * each gpio bank may cover up to two IRQ banks.
+ */
+ if (!chips[gpiobank].irqbase) {
+ chips[gpiobank].irqbase = irq;
+ chips[gpiobank].nirq = 0;
+ }
+
/* set up all irqs in this bank */
set_irq_chained_handler(bank_irq, gpio_irq_handler);
set_irq_chip_data(bank_irq, g);
@@ -309,6 +332,7 @@ static int __init davinci_gpio_irq_setup
set_irq_handler(irq, handle_simple_irq);
set_irq_flags(irq, IRQF_VALID);
}
+ chips[gpiobank].nirq += i;
binten |= BIT(bank);
}
@@ -322,4 +346,4 @@ static int __init davinci_gpio_irq_setup
return 0;
}
-arch_initcall(davinci_gpio_irq_setup);
+core_initcall(davinci_gpio_irq_setup);
--- a/arch/arm/mach-davinci/include/mach/gpio.h
+++ b/arch/arm/mach-davinci/include/mach/gpio.h
@@ -141,21 +141,11 @@ static inline int gpio_cansleep(unsigned
return __gpio_cansleep(gpio);
}
-static inline int gpio_to_irq(unsigned gpio)
-{
- struct davinci_soc_info *soc_info = davinci_get_soc_info();
-
- if (gpio >= DAVINCI_N_GPIO)
- return -EINVAL;
- return soc_info->intc_irq_num + gpio;
-}
+#define gpio_to_irq __gpio_to_irq
static inline int irq_to_gpio(unsigned irq)
{
- struct davinci_soc_info *soc_info = davinci_get_soc_info();
-
- /* caller guarantees gpio_to_irq() succeeded */
- return irq - soc_info->intc_irq_num;
+ return -EOPNOTSUPP;
}
#endif /* __DAVINCI_GPIO_H */
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