This patch seems to get me much more reliable performance using the GPIO banked interrupts on dm355 for the dm9000 driver.
Changes include: - init GPIO handling along with normal GPIO init - mask the level-sensitive bank IRQ during handling - use genirq edge_handler and mask/unmask hooks instead of enable/disable Signed-off-by: Kevin Hilman <[email protected]> --- arch/arm/mach-davinci/gpio.c | 10 ++++++---- 1 files changed, 6 insertions(+), 4 deletions(-) diff --git a/arch/arm/mach-davinci/gpio.c b/arch/arm/mach-davinci/gpio.c index 5310519..9e7c90e 100644 --- a/arch/arm/mach-davinci/gpio.c +++ b/arch/arm/mach-davinci/gpio.c @@ -44,6 +44,7 @@ static struct gpio_controller *__iomem __init gpio2controller(unsigned gpio) return __gpio_to_controller(gpio); } +static int __init davinci_gpio_irq_setup(void); /*--------------------------------------------------------------------------*/ @@ -149,6 +150,7 @@ static int __init davinci_gpio_setup(void) gpiochip_add(&chips[i].chip); } + davinci_gpio_irq_setup(); return 0; } pure_initcall(davinci_gpio_setup); @@ -214,8 +216,8 @@ static int gpio_irq_type(unsigned irq, unsigned trigger) static struct irq_chip gpio_irqchip = { .name = "GPIO", - .enable = gpio_irq_enable, - .disable = gpio_irq_disable, + .unmask = gpio_irq_enable, + .mask = gpio_irq_disable, .set_type = gpio_irq_type, }; @@ -226,10 +228,11 @@ gpio_irq_handler(unsigned irq, struct irq_desc *desc) u32 mask = 0xffff; /* we only care about one bank */ - if (irq & 1) + if (irq & 1) /* FIXME: depends on GPIO bank 0 IRQ being even */ mask <<= 16; /* temporarily mask (level sensitive) parent IRQ */ + desc->chip->mask(irq); desc->chip->ack(irq); while (1) { u32 status; @@ -322,4 +325,3 @@ static int __init davinci_gpio_irq_setup(void) return 0; } -arch_initcall(davinci_gpio_irq_setup); -- 1.6.2.2 _______________________________________________ Davinci-linux-open-source mailing list [email protected] http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source
